linux-toradex.git/drivers/pci/controller/cadence, branch v6.11-rc7

Merge branch 'pci/controller/dwc'

2024-05-16T23:14:12+00:00

- Move DBI accesses from dw_pcie_ep_init() to dw_pcie_ep_init_complete() so
  drivers for endpoints that require Refclk for DBI access, e.g., qcom and
  tegra194, can control when this happens (Manivannan Sadhasivam)

- Add endpoint API kernel-doc (Manivannan Sadhasivam)

- Remove .deinit() callback and instead call rcar_gen4_pcie_ep_deinit()
  explicitly from rcar-gen4, which was the only user (Manivannan
  Sadhasivam)

- Rename dw_pcie_ep_exit() to dw_pcie_ep_deinit() to correspond with
  dw_pcie_ep_init() (Manivannan Sadhasivam)

- Add dw_pcie_ep_cleanup() for drivers that need to clean up eDMA resources
  when PERST# is asserted, e.g., qcom, tegra194 (Manivannan Sadhasivam)

- Rename dw_pcie_ep_init_complete() to dw_pcie_ep_init_registers() to
  better reflect the functionality (Manivannan Sadhasivam)

- Call dw_pcie_ep_init_registers() directly from drivers instead of from
  dw_pcie_ep_init() so drivers, e.g., qcom and tegra194, can do it when
  Refclk is available (Manivannan Sadhasivam)

- Remove the "core_init_notifier" flag, which previously identified drivers
  that required Refclk before DBI access, because it's now unnecessary
  (Manivannan Sadhasivam)

* pci/controller/dwc:
  PCI: endpoint: Remove "core_init_notifier" flag
  PCI: dwc: ep: Call dw_pcie_ep_init_registers() API directly from all glue drivers
  PCI: dwc: ep: Rename dw_pcie_ep_init_complete() to dw_pcie_ep_init_registers()
  PCI: dwc: ep: Introduce dw_pcie_ep_cleanup() API for drivers supporting PERST#
  PCI: dwc: ep: Rename dw_pcie_ep_exit() to dw_pcie_ep_deinit()
  PCI: dwc: ep: Remove deinit() callback from struct dw_pcie_ep_ops
  PCI: dwc: ep: Add Kernel-doc comments for APIs
  PCI: dwc: ep: Fix DBI access failure for drivers requiring refclk from host

PCI: endpoint: Remove "core_init_notifier" flag

2024-04-10T17:52:42+00:00

"core_init_notifier" flag is set by the glue drivers requiring refclk from
the host to complete the DWC core initialization. Also, those drivers will
send a notification to the EPF drivers once the initialization is fully
completed using the pci_epc_init_notify() API. Only then, the EPF drivers
will start functioning.

For the rest of the drivers generating refclk locally, EPF drivers will
start functioning post binding with them. EPF drivers rely on the
'core_init_notifier' flag to differentiate between the drivers.
Unfortunately, this creates two different flows for the EPF drivers.

So to avoid that, let's get rid of the "core_init_notifier" flag and follow
a single initialization flow for the EPF drivers. This is done by calling
the dw_pcie_ep_init_notify() from all glue drivers after the completion of
dw_pcie_ep_init_registers() API. This will allow all the glue drivers to
send the notification to the EPF drivers once the initialization is fully
completed.

Only difference here is that, the drivers requiring refclk from host will
send the notification once refclk is received, while others will send it
during probe time itself.

But this also requires the EPC core driver to deliver the notification
after EPF driver bind. Because, the glue driver can send the notification
before the EPF drivers bind() and in those cases the EPF drivers will miss
the event. To accommodate this, EPC core is now caching the state of the
EPC initialization in 'init_complete' flag and pci-ep-cfs driver sends the
notification to EPF drivers based on that after each EPF driver bind.

Link: https://lore.kernel.org/linux-pci/20240327-pci-dbi-rework-v12-8-082625472414@linaro.org
Tested-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
Signed-off-by: Krzysztof Wilczyński
Reviewed-by: Frank Li
Reviewed-by: Niklas Cassel

PCI: cadence: Set a 64-bit BAR if requested

2024-04-10T17:31:16+00:00

Ever since commit f25b5fae29d4 ("PCI: endpoint: Setting a BAR size > 4 GB
is invalid if 64-bit flag is not set") it has been impossible to get the
.set_bar() callback with a BAR size > 2 GB (yes, 2GB!), if the BAR was
also not requested to be configured as a 64-bit BAR.

Thus, forcing setting the 64-bit flag for BARs larger than 2 GB in the
lower level driver is dead code and can be removed.

It is however possible that an EPF driver configures a BAR as 64-bit,
even if the requested size is < 4 GB.

Respect the requested BAR configuration, just like how it is already
respected with regards to the prefetchable bit.

Link: https://lore.kernel.org/linux-pci/20240320113157.322695-7-cassel@kernel.org
Signed-off-by: Niklas Cassel 
Signed-off-by: Krzysztof Wilczyński 
Reviewed-by: Manivannan Sadhasivam

PCI: cadence: Clear the ARI Capability Next Function Number of the last function

2024-03-10T18:33:16+00:00

Next Function Number field in ARI Capability Register for last function
must be zero by default as per the PCIe specification, indicating there
is no next higher number function but that's not happening in our case,
so this patch clears the Next Function Number field for last function
used.

[kwilczynski: white spaces update for one define]
Link: https://lore.kernel.org/linux-pci/20231202085015.3048516-1-s-vadapalli@ti.com
Signed-off-by: Jasko-EXT Wojciech 
Signed-off-by: Achal Verma 
Signed-off-by: Siddharth Vadapalli 
Signed-off-by: Krzysztof Wilczyński 
Reviewed-by: Vignesh Raghavendra

Merge branch 'pci/irq-clean-up'

2024-01-15T18:10:40+00:00

- Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX to be more explicit and match spec
  terminology (Bjorn Helgaas)

- Use existing PCI_IRQ_INTX, PCI_IRQ_MSI, PCI_IRQ_MSIX in artpec6, cadence,
  designware, designware-plat, dra7xx, imx6, keembay, keystone, layerscape,
  mhi, ntb, qcom, rcar, rcar-gen4, rockchip, tegra194, uniphier, vntb; drop
  the redundant pci_epc_irq_type enum with the same values (Damien Le Moal)

- Use "intx" instead of "leg" or "legacy" when describing INTx interrupts
  in endpoint core, endpoint tests, cadence, dra7xx, designware,
  dw-rockchip, dwc core, imx6, keystone, layerscape, qcom, rcar-gen4,
  rockchip, tegra194, uniphier, xilinx-nwl (Damien Le Moal)

* pci/irq-clean-up:
  PCI: xilinx-nwl: Use INTX instead of legacy
  PCI: rockchip-host: Rename rockchip_pcie_legacy_int_handler()
  PCI: rockchip-ep: Use INTX instead of legacy
  PCI: uniphier: Use INTX instead of legacy
  PCI: tegra194: Use INTX instead of legacy
  PCI: dw-rockchip: Rename rockchip_pcie_legacy_int_handler()
  PCI: keystone: Use INTX instead of legacy
  PCI: dwc: Rename dw_pcie_ep_raise_legacy_irq()
  PCI: cadence: Use INTX instead of legacy
  PCI: dra7xx: Rename dra7xx_pcie_raise_legacy_irq()
  misc: pci_endpoint_test: Use INTX instead of LEGACY
  PCI: endpoint: Rename LEGACY to INTX in test function driver
  PCI: endpoint: Use INTX instead of legacy
  PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitions
  PCI: Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX

PCI: j721e: Make TI J721E depend on ARCH_K3

2024-01-06T04:51:51+00:00

The J721E PCIe is hardware specific to TI SoC parts so add a dependency
on that so it's available for those SoC parts and for compile testing but
not necessarily everyone who enables the Cadence PCIe controller.

Link: https://lore.kernel.org/linux-pci/20240104213910.1426843-1-pbrobinson@gmail.com
Signed-off-by: Peter Robinson 
Signed-off-by: Krzysztof Wilczyński

PCI: j721e: Add TI J784S4 PCIe configuration

2024-01-06T04:50:49+00:00

Add PCIe configuration for J784S4 SoC platform which has 4x lane
support.

Link: https://lore.kernel.org/linux-pci/20231128054402.2155183-6-s-vadapalli@ti.com
Tested-by: Achal Verma 
Signed-off-by: Matt Ranostay 
Signed-off-by: Achal Verma 
Signed-off-by: Siddharth Vadapalli 
Signed-off-by: Krzysztof Wilczyński 
Reviewed-by: Roger Quadros

PCI: cadence: Use INTX instead of legacy

2023-12-19T08:36:42+00:00

In the Cadence endpoint controller driver, rename the function
cdns_pcie_ep_send_legacy_irq() to cdns_pcie_ep_send_intx_irq() to match
the macro PCI_IRQ_INTX name. Related comments and messages mentioning
"legacy" are also changed to refer to "intx".

Link: https://lore.kernel.org/r/20231122060406.14695-9-dlemoal@kernel.org
Signed-off-by: Damien Le Moal 
Signed-off-by: Lorenzo Pieralisi 
Reviewed-by: Christoph Hellwig

PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitions

2023-12-18T10:55:56+00:00

linux/pci.h defines the IRQ flags PCI_IRQ_INTX, PCI_IRQ_MSI and
PCI_IRQ_MSIX. Let's use these flags directly instead of the endpoint
definitions provided by enum pci_epc_irq_type. This removes the need
for defining this enum type completely.

Link: https://lore.kernel.org/r/20231122060406.14695-3-dlemoal@kernel.org
Signed-off-by: Damien Le Moal 
Signed-off-by: Lorenzo Pieralisi 
Reviewed-by: Serge Semin 
Reviewed-by: Christoph Hellwig 
Acked-by: Manivannan Sadhasivam

PCI: j721e: Add PCIe 4x lane selection support

2023-12-13T18:26:51+00:00

Add support for setting of two-bit field that allows selection of 4x lane
PCIe which was previously limited to only 2x lanes.

Link: https://lore.kernel.org/linux-pci/20231128054402.2155183-5-s-vadapalli@ti.com
Signed-off-by: Matt Ranostay 
Signed-off-by: Achal Verma 
Signed-off-by: Siddharth Vadapalli 
Signed-off-by: Krzysztof Wilczyński 
Reviewed-by: Vignesh Raghavendra 
Reviewed-by: Roger Quadros