linux-toradex.git/drivers/pci/endpoint/functions, branch v5.0

pci-epf-test/pci_endpoint_test: Add MSI-X support

2018-07-19T10:46:45+00:00

Add MSI-X support and update driver documentation accordingly.

Signed-off-by: Gustavo Pimentel 
Signed-off-by: Lorenzo Pieralisi 
Acked-by: Kishon Vijay Abraham I

pci-epf-test/pci_endpoint_test: Cleanup PCI_ENDPOINT_TEST memspace

2018-07-19T10:39:44+00:00

Cleanup PCI_ENDPOINT_TEST memspace (by moving the interrupt number away
from command section).

Add IRQ_TYPE register to identify the triggered ID interrupt required
for the READ/WRITE/COPY tests and raise IRQ test commands.

Update documentation accordingly.

Signed-off-by: Gustavo Pimentel 
Signed-off-by: Lorenzo Pieralisi 
Acked-by: Kishon Vijay Abraham I

Merge branch 'lorenzo/pci/endpoint'

2018-06-06T21:10:30+00:00

  - use usleep() instead of mdelay() in endpoint test (Jia-Ju Bai)

  - add configfs entries for pci_epf_driver device IDs (Kishon Vijay
    Abraham I)

  - clean up pci_endpoint_test driver (Gustavo Pimentel)

* lorenzo/pci/endpoint:
  PCI: endpoint: Create configfs entry for each pci_epf_device_id table entry
  misc: pci_endpoint_test: Use pci_irq_vector function
  PCI: endpoint: functions/pci-epf-test: Replace lower into upper case characters
  misc: pci_endpoint_test: Replace lower into upper case characters
  PCI: endpoint: Replace mdelay with usleep_range() in pci_epf_test_write()

PCI: dwc: Add support for EP mode

2018-05-15T14:51:38+00:00

The PCIe controller dual mode is capable of operating in Root Complex
(RC) mode as well as EP mode by configuration option.

Add EP support to the DesignWare driver on top of RC mode support.

Add new property on pci_epc structure which allow to configure
pci_epf_test driver accordingly to the controller specific requirements.

Signed-off-by: Gustavo Pimentel 
Signed-off-by: Lorenzo Pieralisi 
Acked-by: Kishon Vijay Abraham I

PCI: endpoint: functions/pci-epf-test: Replace lower into upper case characters

2018-05-15T14:13:10+00:00

Replace all initial lower case character into upper case in comments
and debug printks.

Signed-off-by: Gustavo Pimentel 
Signed-off-by: Lorenzo Pieralisi

PCI: endpoint: Replace mdelay with usleep_range() in pci_epf_test_write()

2018-05-08T10:13:42+00:00

pci_epf_test_write() is never called in atomic context.

The call chain ending up at pci_epf_test_write() is:
[1] pci_epf_test_write() <- pci_epf_test_cmd_handler()

pci_epf_test_cmd_handler() is set as a parameter of INIT_DELAYED_WORK()
in pci_epf_test_probe().
This function is not called in atomic context.

Despite never getting called from atomic context, pci_epf_test_write()
calls mdelay() to busy wait.

This is not necessary and can be replaced with usleep_range() to
avoid busy waiting.

Signed-off-by: Jia-Ju Bai 
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi 
Acked-by: Kishon Vijay Abraham I

PCI: endpoint: Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar

2018-04-03T11:38:05+00:00

Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar.

This is needed so that epc->ops->clear_bar() can clear the BAR pair,
if the BAR is 64-bits wide.

This also makes it possible for pci_epc_clear_bar() to sanity check
the flags.

Signed-off-by: Niklas Cassel 
Signed-off-by: Lorenzo Pieralisi 
Reviewed-by: Gustavo Pimentel

PCI: endpoint: Handle 64-bit BARs properly

2018-04-03T11:38:04+00:00

If a 64-bit BAR was set-up, we need to skip a BAR,
since a 64-bit BAR consists of a BAR pair.

We need to check what BAR width the epc->ops->set_bar() specific
implementation actually did set-up, since some drivers, like the
Cadence EP controller, sometimes sets up a 64-bit BAR, even though
a 32-bit BAR was requested.

Signed-off-by: Niklas Cassel 
Signed-off-by: Lorenzo Pieralisi 
Acked-by: Kishon Vijay Abraham I

PCI: endpoint: Simplify epc->ops->set_bar()/pci_epc_set_bar()

2018-04-03T11:23:38+00:00

Add barno and flags to struct epf_bar.
That way we can simplify epc->ops->set_bar()/pci_epc_set_bar()
by passing a struct *epf_bar instead of a whole lot of arguments.

This is needed so that epc->ops->set_bar() implementations can
modify BAR flags. Will be utilized in a succeeding patch.

Signed-off-by: Niklas Cassel 
Signed-off-by: Lorenzo Pieralisi 
Reviewed-by: Gustavo Pimentel 
Acked-by: Kishon Vijay Abraham I

PCI: endpoint: BAR width should not depend on sizeof dma_addr_t

2018-04-03T11:23:30+00:00

If a BAR supports 64-bit width or not depends on the hardware,
and should thus not depend on sizeof(dma_addr_t).

If a certain hardware doesn't support 64-bit BARs, its
epc->ops->set_bar() implementation should return -EINVAL
when PCI_BASE_ADDRESS_MEM_TYPE_64 is set.

We can't change pci_epc_set_bar() to only set
PCI_BASE_ADDRESS_MEM_TYPE_64 based on size, since if the user,
for some reason, wants to configure a BAR with a 64-bit width,
even though the BAR size is less than 4 GB, he should be able
to do that.

However, since pci-epf-test is simply a test and not an API,
we can set PCI_BASE_ADDRESS_MEM_TYPE_64 in pci-epf-test itself
only based on size.

Signed-off-by: Niklas Cassel 
Signed-off-by: Lorenzo Pieralisi 
Acked-by: Kishon Vijay Abraham I