<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/drivers/pci/msi, branch master</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>Merge tag 'irq-msi-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip</title>
<updated>2026-02-11T00:30:29+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-02-11T00:30:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=3381d7b2b3dd012d366b9ba9339f98d54bea69fd'/>
<id>3381d7b2b3dd012d366b9ba9339f98d54bea69fd</id>
<content type='text'>
Pull MSI updates from Thomas Gleixner:
 "Updates for the [PCI] MSI subsystem:

   - Add interrupt redirection infrastructure

     Some PCI controllers use a single demultiplexing interrupt for the
     MSI interrupts of subordinate devices.

     This prevents setting the interrupt affinity of device interrupts,
     which causes device interrupts to be delivered to a single CPU.
     That obviously is counterproductive for multi-queue devices and
     interrupt balancing.

     To work around this limitation the new infrastructure installs a
     dummy irq_set_affinity() callback which captures the affinity mask
     and picks a redirection target CPU out of the mask.

     When the PCI controller demultiplexes the interrupts it invokes a
     new handling function in the core, which either runs the interrupt
     handler in the context of the target CPU or delegates it to
     irq_work on the target CPU.

   - Utilize the interrupt redirection mechanism in the PCI DWC host
     controller driver.

     This allows affinity control for the subordinate device MSI
     interrupts instead of being randomly executed on the CPU which runs
     the demultiplex handler.

   - Replace the binary 64-bit MSI flag with a DMA mask

     Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability,
     but implement less than 64 address bits. This breaks on platforms
     where such a device is assigned an MSI address higher than what's
     supported.

     With the binary 64-bit flag there is no other choice than disabling
     64-bit MSI support which leaves the device disfunctional.

     By using a DMA mask the address limit of a device can be described
     correctly which provides support for the above scenario.

   - Make use of the DMA mask based address limit in the hda/intel and
     radeon drivers to enable them on affected platforms

   - The usual small cleanups and improvements"

* tag 'irq-msi-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  ALSA: hda/intel: Make MSI address limit based on the device DMA limit
  drm/radeon: Make MSI address limit based on the device DMA limit
  PCI/MSI: Check the device specific address mask in msi_verify_entries()
  PCI/MSI: Convert the boolean no_64bit_msi flag to a DMA address mask
  genirq/redirect: Prevent writing MSI message on affinity change
  PCI/MSI: Unmap MSI-X region on error
  genirq: Update effective affinity for redirected interrupts
  PCI: dwc: Enable MSI affinity support
  PCI: dwc: Code cleanup
  genirq: Add interrupt redirection infrastructure
  genirq/msi: Correct kernel-doc in &lt;linux/msi.h&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull MSI updates from Thomas Gleixner:
 "Updates for the [PCI] MSI subsystem:

   - Add interrupt redirection infrastructure

     Some PCI controllers use a single demultiplexing interrupt for the
     MSI interrupts of subordinate devices.

     This prevents setting the interrupt affinity of device interrupts,
     which causes device interrupts to be delivered to a single CPU.
     That obviously is counterproductive for multi-queue devices and
     interrupt balancing.

     To work around this limitation the new infrastructure installs a
     dummy irq_set_affinity() callback which captures the affinity mask
     and picks a redirection target CPU out of the mask.

     When the PCI controller demultiplexes the interrupts it invokes a
     new handling function in the core, which either runs the interrupt
     handler in the context of the target CPU or delegates it to
     irq_work on the target CPU.

   - Utilize the interrupt redirection mechanism in the PCI DWC host
     controller driver.

     This allows affinity control for the subordinate device MSI
     interrupts instead of being randomly executed on the CPU which runs
     the demultiplex handler.

   - Replace the binary 64-bit MSI flag with a DMA mask

     Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability,
     but implement less than 64 address bits. This breaks on platforms
     where such a device is assigned an MSI address higher than what's
     supported.

     With the binary 64-bit flag there is no other choice than disabling
     64-bit MSI support which leaves the device disfunctional.

     By using a DMA mask the address limit of a device can be described
     correctly which provides support for the above scenario.

   - Make use of the DMA mask based address limit in the hda/intel and
     radeon drivers to enable them on affected platforms

   - The usual small cleanups and improvements"

* tag 'irq-msi-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  ALSA: hda/intel: Make MSI address limit based on the device DMA limit
  drm/radeon: Make MSI address limit based on the device DMA limit
  PCI/MSI: Check the device specific address mask in msi_verify_entries()
  PCI/MSI: Convert the boolean no_64bit_msi flag to a DMA address mask
  genirq/redirect: Prevent writing MSI message on affinity change
  PCI/MSI: Unmap MSI-X region on error
  genirq: Update effective affinity for redirected interrupts
  PCI: dwc: Enable MSI affinity support
  PCI: dwc: Code cleanup
  genirq: Add interrupt redirection infrastructure
  genirq/msi: Correct kernel-doc in &lt;linux/msi.h&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>PCI/MSI: Check the device specific address mask in msi_verify_entries()</title>
<updated>2026-01-31T00:11:48+00:00</updated>
<author>
<name>Vivian Wang</name>
<email>wangruikang@iscas.ac.cn</email>
</author>
<published>2026-01-29T01:56:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=52f0d862f595a2fa18ef44532619a080c24fe4cb'/>
<id>52f0d862f595a2fa18ef44532619a080c24fe4cb</id>
<content type='text'>
Instead of a 32-bit/64-bit dichotomy, check the MSI address against
the device specific address mask.

This allows platforms with an MSI doorbell address above the 32-bit limit
to work with devices without full 64-bit MSI address support, as long as
the doorbell is within the addressable range of the device.

[ tglx: Massaged changelog ]

Signed-off-by: Vivian Wang &lt;wangruikang@iscas.ac.cn&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Reviewed-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-2-70da998f2750@iscas.ac.cn
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Instead of a 32-bit/64-bit dichotomy, check the MSI address against
the device specific address mask.

This allows platforms with an MSI doorbell address above the 32-bit limit
to work with devices without full 64-bit MSI address support, as long as
the doorbell is within the addressable range of the device.

[ tglx: Massaged changelog ]

Signed-off-by: Vivian Wang &lt;wangruikang@iscas.ac.cn&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Reviewed-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-2-70da998f2750@iscas.ac.cn
</pre>
</div>
</content>
</entry>
<entry>
<title>PCI/MSI: Convert the boolean no_64bit_msi flag to a DMA address mask</title>
<updated>2026-01-31T00:11:48+00:00</updated>
<author>
<name>Vivian Wang</name>
<email>wangruikang@iscas.ac.cn</email>
</author>
<published>2026-01-29T01:56:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=386ced19e9a348e8131d20f009e692fa8fcc4568'/>
<id>386ced19e9a348e8131d20f009e692fa8fcc4568</id>
<content type='text'>
Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
implement less than 64 address bits. This breaks on platforms where such
a device is assigned an MSI address higher than what's supported.

Currently, no_64bit_msi bit is set for these devices, meaning that only
32-bit MSI addresses are allowed for them. However, on some platforms the
MSI doorbell address is above the 32-bit limit but within the addressable
range of the device.

As a first step to enable MSI on those combinations of devices and
platforms, convert the boolean no_64bit_msi flag to a DMA mask and fixup
the affected usage sites:

  - no_64bit_msi = 1    -&gt;    msi_addr_mask = DMA_BIT_MASK(32)
  - no_64bit_msi = 0    -&gt;    msi_addr_mask = DMA_BIT_MASK(64)
  - if (no_64bit_msi)   -&gt;    if (msi_addr_mask &lt; DMA_BIT_MASK(64))

Since no values other than DMA_BIT_MASK(32) and DMA_BIT_MASK(64) are used,
this is functionally equivalent.

This prepares for changing the binary decision between 32 and 64 bit to a
DMA mask based decision which allows to support systems which have a DMA
address space less than 64bit but a MSI doorbell address above the 32-bit
limit.

[ tglx: Massaged changelog ]

Signed-off-by: Vivian Wang &lt;wangruikang@iscas.ac.cn&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Reviewed-by: Brett Creeley &lt;brett.creeley@amd.com&gt; # ionic
Reviewed-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Acked-by: Takashi Iwai &lt;tiwai@suse.de&gt; # sound
Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-1-70da998f2750@iscas.ac.cn
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
implement less than 64 address bits. This breaks on platforms where such
a device is assigned an MSI address higher than what's supported.

Currently, no_64bit_msi bit is set for these devices, meaning that only
32-bit MSI addresses are allowed for them. However, on some platforms the
MSI doorbell address is above the 32-bit limit but within the addressable
range of the device.

As a first step to enable MSI on those combinations of devices and
platforms, convert the boolean no_64bit_msi flag to a DMA mask and fixup
the affected usage sites:

  - no_64bit_msi = 1    -&gt;    msi_addr_mask = DMA_BIT_MASK(32)
  - no_64bit_msi = 0    -&gt;    msi_addr_mask = DMA_BIT_MASK(64)
  - if (no_64bit_msi)   -&gt;    if (msi_addr_mask &lt; DMA_BIT_MASK(64))

Since no values other than DMA_BIT_MASK(32) and DMA_BIT_MASK(64) are used,
this is functionally equivalent.

This prepares for changing the binary decision between 32 and 64 bit to a
DMA mask based decision which allows to support systems which have a DMA
address space less than 64bit but a MSI doorbell address above the 32-bit
limit.

[ tglx: Massaged changelog ]

Signed-off-by: Vivian Wang &lt;wangruikang@iscas.ac.cn&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Reviewed-by: Brett Creeley &lt;brett.creeley@amd.com&gt; # ionic
Reviewed-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Acked-by: Takashi Iwai &lt;tiwai@suse.de&gt; # sound
Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-1-70da998f2750@iscas.ac.cn
</pre>
</div>
</content>
</entry>
<entry>
<title>irqchip/gic-v5: Add ACPI ITS probing</title>
<updated>2026-01-27T14:31:42+00:00</updated>
<author>
<name>Lorenzo Pieralisi</name>
<email>lpieralisi@kernel.org</email>
</author>
<published>2026-01-15T09:50:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=a97efa5ba594642b86fb6702f38ed0d18e3b0269'/>
<id>a97efa5ba594642b86fb6702f38ed0d18e3b0269</id>
<content type='text'>
On ACPI ARM64 systems the GICv5 ITS configuration and translate frames
are described in the MADT table.

Refactor the current GICv5 ITS driver code to share common functions
between ACPI and OF and implement ACPI probing in the GICv5 ITS driver.

Add iort_msi_xlate() to map a device ID and retrieve an MSI controller
fwnode node for ACPI systems and update pci_msi_map_rid_ctlr_node() to
use it in its ACPI code path.

Add the required functions to IORT code for deviceID retrieval and IRQ
domain registration and look-up so that the GICv5 ITS driver in an
ACPI based system can be successfully probed.

Signed-off-by: Lorenzo Pieralisi &lt;lpieralisi@kernel.org&gt;
Reviewed-by: Jonathan Cameron &lt;jonathan.cameron@huawei.com&gt;
Acked-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Link: https://patch.msgid.link/20260115-gicv5-host-acpi-v3-5-c13a9a150388@kernel.org
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
On ACPI ARM64 systems the GICv5 ITS configuration and translate frames
are described in the MADT table.

Refactor the current GICv5 ITS driver code to share common functions
between ACPI and OF and implement ACPI probing in the GICv5 ITS driver.

Add iort_msi_xlate() to map a device ID and retrieve an MSI controller
fwnode node for ACPI systems and update pci_msi_map_rid_ctlr_node() to
use it in its ACPI code path.

Add the required functions to IORT code for deviceID retrieval and IRQ
domain registration and look-up so that the GICv5 ITS driver in an
ACPI based system can be successfully probed.

Signed-off-by: Lorenzo Pieralisi &lt;lpieralisi@kernel.org&gt;
Reviewed-by: Jonathan Cameron &lt;jonathan.cameron@huawei.com&gt;
Acked-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Link: https://patch.msgid.link/20260115-gicv5-host-acpi-v3-5-c13a9a150388@kernel.org
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>PCI/MSI: Make the pci_msi_map_rid_ctlr_node() interface firmware agnostic</title>
<updated>2026-01-27T14:31:42+00:00</updated>
<author>
<name>Lorenzo Pieralisi</name>
<email>lpieralisi@kernel.org</email>
</author>
<published>2026-01-15T09:50:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=a08df2fbba47be20b5769b054d9a19ddee567bdc'/>
<id>a08df2fbba47be20b5769b054d9a19ddee567bdc</id>
<content type='text'>
To support booting with OF and ACPI seamlessly, GIC ITS parent code
requires the PCI/MSI irqdomain layer to implement a function to retrieve
an MSI controller fwnode and map an RID in a firmware agnostic way
(ie pci_msi_map_rid_ctlr_node()).

Convert pci_msi_map_rid_ctlr_node() to an OF agnostic interface
(fwnode_handle based) and update the GIC ITS MSI parent code to reflect
the pci_msi_map_rid_ctlr_node() change.

Signed-off-by: Lorenzo Pieralisi &lt;lpieralisi@kernel.org&gt;
Reviewed-by: Jonathan Cameron &lt;jonathan.cameron@huawei.com&gt;
Acked-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Link: https://patch.msgid.link/20260115-gicv5-host-acpi-v3-2-c13a9a150388@kernel.org
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
To support booting with OF and ACPI seamlessly, GIC ITS parent code
requires the PCI/MSI irqdomain layer to implement a function to retrieve
an MSI controller fwnode and map an RID in a firmware agnostic way
(ie pci_msi_map_rid_ctlr_node()).

Convert pci_msi_map_rid_ctlr_node() to an OF agnostic interface
(fwnode_handle based) and update the GIC ITS MSI parent code to reflect
the pci_msi_map_rid_ctlr_node() change.

Signed-off-by: Lorenzo Pieralisi &lt;lpieralisi@kernel.org&gt;
Reviewed-by: Jonathan Cameron &lt;jonathan.cameron@huawei.com&gt;
Acked-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Link: https://patch.msgid.link/20260115-gicv5-host-acpi-v3-2-c13a9a150388@kernel.org
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>PCI/MSI: Unmap MSI-X region on error</title>
<updated>2026-01-26T08:46:48+00:00</updated>
<author>
<name>Haoxiang Li</name>
<email>lihaoxiang@isrc.iscas.ac.cn</email>
</author>
<published>2026-01-25T14:44:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=1a8d4c6ecb4c81261bcdf13556abd4a958eca202'/>
<id>1a8d4c6ecb4c81261bcdf13556abd4a958eca202</id>
<content type='text'>
msix_capability_init() fails to unmap the MSI-X region if
msix_setup_interrupts() fails.

Add the missing iounmap() for that error path.

[ tglx: Massaged change log ]

Signed-off-by: Haoxiang Li &lt;lihaoxiang@isrc.iscas.ac.cn&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Link: https://patch.msgid.link/20260125144452.2103812-1-lihaoxiang@isrc.iscas.ac.cn
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
msix_capability_init() fails to unmap the MSI-X region if
msix_setup_interrupts() fails.

Add the missing iounmap() for that error path.

[ tglx: Massaged change log ]

Signed-off-by: Haoxiang Li &lt;lihaoxiang@isrc.iscas.ac.cn&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Link: https://patch.msgid.link/20260125144452.2103812-1-lihaoxiang@isrc.iscas.ac.cn
</pre>
</div>
</content>
</entry>
<entry>
<title>PCI/MSI: Delete pci_msi_create_irq_domain()</title>
<updated>2025-10-16T19:09:52+00:00</updated>
<author>
<name>Nam Cao</name>
<email>namcao@linutronix.de</email>
</author>
<published>2025-07-21T06:36:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=dce745009349fc391271c9415d5e242781ddadd7'/>
<id>dce745009349fc391271c9415d5e242781ddadd7</id>
<content type='text'>
pci_msi_create_irq_domain() is now unused. Delete it.

Signed-off-by: Nam Cao &lt;namcao@linutronix.de&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
pci_msi_create_irq_domain() is now unused. Delete it.

Signed-off-by: Nam Cao &lt;namcao@linutronix.de&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'devicetree-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux</title>
<updated>2025-10-01T23:58:24+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2025-10-01T23:58:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=9792d660a4e91d31a6b1af105ae3f1c29107e94b'/>
<id>9792d660a4e91d31a6b1af105ae3f1c29107e94b</id>
<content type='text'>
Pull devicetree updates from Rob Herring:
 "DT core:

   - Update dtc to upstream version v1.7.2-35-g52f07dcca47c

   - Add stub for of_get_next_child_with_prefix()

   - Convert of_msi_map_id() callers to of_msi_xlate()

 DT bindings:

   - Convert multiple text board bindings to DT schema format

   - Add bindings for synaptics,synaptics_i2c touchscreen controller,
     innolux,n133hse-ea1 and nlt,nl12880bc20-spwg-24 displays, and NXP
     vf610 reboot controller

   - Add new Arm Cortex-A320/A520AE/A720AE and C1-Nano/Pro/Premium/Ultra
     CPUs. Add missing Applied Micro CPU compatibles. Add pu-supply and
     fsl,soc-operating-points properties for CPU nodes.

   - Add QCom Glymur PDC and tegra264-agic interrupt controllers

   - Add samsung,exynos8890-mali GPU to Arm Mali Midgard

   - Drop Samsung S3C2410 display related bindings

   - Allow separate DP lane and AUX connections in dp-connector

   - Add some missing, undocumented vendor prefixes

   - Add missing '#address-cells' properties in interrupt controller
     bindings which dtc now warns about

   - Drop duplicate socfpga-sdram-edac.txt, moxa,moxart-watchdog.txt,
     fsl/mpic.txt, ti,opa362.txt, and cavium-thunder2.txt legacy text
     bindings which are already covered by existing schemas.

   - Various binding fixes for Mediatek platforms in mailbox, regulator,
     pinctrl, timer, and display

   - Drop work-around for yamllint quoting of values containing ','

   - Various spelling, typo, grammar, and duplicated words fixes in DT
     bindings and docs

   - Add binding guidelines for defining properties at top level of
     schemas, lack of node name ABI, and usage of simple-mfd"

* tag 'devicetree-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (81 commits)
  dt-bindings: arm: altera: Drop socfpga-sdram-edac.txt
  dt-bindings: gpu: Convert nvidia,gk20a to DT schema
  dt-bindings: rng: sparc_sun_oracle_rng: convert to DT schema
  dt-bindings: vendor-prefixes: update regex for properties without a prefix
  dt-bindings: display: bridge: convert megachips-stdpxxxx-ge-b850v3-fw.txt to yaml
  scripts: dt_to_config: fix grammar and a typo in --help text
  dt-bindings: fix spelling, typos, grammar, duplicated words
  docs: dt: fix grammar and spelling
  of: base: Add of_get_next_child_with_prefix() stub
  dt-bindings: trivial-devices: Add compatible string synaptics,synaptics_i2c
  dt-bindings: soc: mediatek: pwrap: Add power-domains property
  dt-bindings: pinctrl: mt65xx: Allow gpio-line-names
  dt-bindings: media: Convert MediaTek mt8173-vpu bindings to DT schema
  dt-bindings: arm: mediatek: Support mt8183-audiosys variant
  dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional
  dt-bindings: regulator: mediatek,mt6331: Add missing compatible
  dt-bindings: regulator: mediatek,mt6331: Fix various regulator names
  dt-bindings: regulator: mediatek,mt6332-regulator: Add missing compatible
  dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing base reg
  dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing pwm_ch7_2
  ...
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull devicetree updates from Rob Herring:
 "DT core:

   - Update dtc to upstream version v1.7.2-35-g52f07dcca47c

   - Add stub for of_get_next_child_with_prefix()

   - Convert of_msi_map_id() callers to of_msi_xlate()

 DT bindings:

   - Convert multiple text board bindings to DT schema format

   - Add bindings for synaptics,synaptics_i2c touchscreen controller,
     innolux,n133hse-ea1 and nlt,nl12880bc20-spwg-24 displays, and NXP
     vf610 reboot controller

   - Add new Arm Cortex-A320/A520AE/A720AE and C1-Nano/Pro/Premium/Ultra
     CPUs. Add missing Applied Micro CPU compatibles. Add pu-supply and
     fsl,soc-operating-points properties for CPU nodes.

   - Add QCom Glymur PDC and tegra264-agic interrupt controllers

   - Add samsung,exynos8890-mali GPU to Arm Mali Midgard

   - Drop Samsung S3C2410 display related bindings

   - Allow separate DP lane and AUX connections in dp-connector

   - Add some missing, undocumented vendor prefixes

   - Add missing '#address-cells' properties in interrupt controller
     bindings which dtc now warns about

   - Drop duplicate socfpga-sdram-edac.txt, moxa,moxart-watchdog.txt,
     fsl/mpic.txt, ti,opa362.txt, and cavium-thunder2.txt legacy text
     bindings which are already covered by existing schemas.

   - Various binding fixes for Mediatek platforms in mailbox, regulator,
     pinctrl, timer, and display

   - Drop work-around for yamllint quoting of values containing ','

   - Various spelling, typo, grammar, and duplicated words fixes in DT
     bindings and docs

   - Add binding guidelines for defining properties at top level of
     schemas, lack of node name ABI, and usage of simple-mfd"

* tag 'devicetree-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (81 commits)
  dt-bindings: arm: altera: Drop socfpga-sdram-edac.txt
  dt-bindings: gpu: Convert nvidia,gk20a to DT schema
  dt-bindings: rng: sparc_sun_oracle_rng: convert to DT schema
  dt-bindings: vendor-prefixes: update regex for properties without a prefix
  dt-bindings: display: bridge: convert megachips-stdpxxxx-ge-b850v3-fw.txt to yaml
  scripts: dt_to_config: fix grammar and a typo in --help text
  dt-bindings: fix spelling, typos, grammar, duplicated words
  docs: dt: fix grammar and spelling
  of: base: Add of_get_next_child_with_prefix() stub
  dt-bindings: trivial-devices: Add compatible string synaptics,synaptics_i2c
  dt-bindings: soc: mediatek: pwrap: Add power-domains property
  dt-bindings: pinctrl: mt65xx: Allow gpio-line-names
  dt-bindings: media: Convert MediaTek mt8173-vpu bindings to DT schema
  dt-bindings: arm: mediatek: Support mt8183-audiosys variant
  dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional
  dt-bindings: regulator: mediatek,mt6331: Add missing compatible
  dt-bindings: regulator: mediatek,mt6331: Fix various regulator names
  dt-bindings: regulator: mediatek,mt6332-regulator: Add missing compatible
  dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing base reg
  dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing pwm_ch7_2
  ...
</pre>
</div>
</content>
</entry>
<entry>
<title>PCI/MSI: Remove the conditional parent [un]mask logic</title>
<updated>2025-09-09T12:44:30+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2025-09-03T14:04:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=ba9d484ed3578705fcd24795b800e8e4364afb8c'/>
<id>ba9d484ed3578705fcd24795b800e8e4364afb8c</id>
<content type='text'>
Now that msi_lib_init_dev_msi_info() overwrites the irq_[un]mask()
callbacks when the MSI_FLAG_PCI_MSI_MASK_PARENT flag is set by the parent
domain, the conditional [un]mask logic is obsolete.

Remove it.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Marc Zyngier &lt;maz@kernel.org&gt;
Acked-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/all/20250903135433.444329373@linutronix.de

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Now that msi_lib_init_dev_msi_info() overwrites the irq_[un]mask()
callbacks when the MSI_FLAG_PCI_MSI_MASK_PARENT flag is set by the parent
domain, the conditional [un]mask logic is obsolete.

Remove it.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Marc Zyngier &lt;maz@kernel.org&gt;
Acked-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/all/20250903135433.444329373@linutronix.de

</pre>
</div>
</content>
</entry>
<entry>
<title>of/irq: Convert of_msi_map_id() callers to of_msi_xlate()</title>
<updated>2025-09-03T14:01:26+00:00</updated>
<author>
<name>Lorenzo Pieralisi</name>
<email>lpieralisi@kernel.org</email>
</author>
<published>2025-08-05T13:34:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=a576a849d5f33356e0d8fd3eae4fbaf8869417e5'/>
<id>a576a849d5f33356e0d8fd3eae4fbaf8869417e5</id>
<content type='text'>
With the introduction of the of_msi_xlate() function, the OF layer
provides an API to map a device ID and retrieve the MSI controller
node the ID is mapped to with a single call.

of_msi_map_id() is currently used to map a deviceID to a specific
MSI controller node; of_msi_xlate() can be used for that purpose
too, there is no need to keep the two functions.

Convert of_msi_map_id() to of_msi_xlate() calls and update the
of_msi_xlate() documentation to describe how the struct device_node
pointer passed in should be set-up to either provide the MSI controller
node target or receive its pointer upon mapping completion.

Signed-off-by: Lorenzo Pieralisi &lt;lpieralisi@kernel.org&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Rob Herring &lt;robh@kernel.org&gt;
Cc: Marc Zyngier &lt;maz@kernel.org&gt;
Acked-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Frank Li &lt;Frank.Li@nxp.com&gt;
Link: https://lore.kernel.org/r/20250805133443.936955-1-lpieralisi@kernel.org
Signed-off-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
With the introduction of the of_msi_xlate() function, the OF layer
provides an API to map a device ID and retrieve the MSI controller
node the ID is mapped to with a single call.

of_msi_map_id() is currently used to map a deviceID to a specific
MSI controller node; of_msi_xlate() can be used for that purpose
too, there is no need to keep the two functions.

Convert of_msi_map_id() to of_msi_xlate() calls and update the
of_msi_xlate() documentation to describe how the struct device_node
pointer passed in should be set-up to either provide the MSI controller
node target or receive its pointer upon mapping completion.

Signed-off-by: Lorenzo Pieralisi &lt;lpieralisi@kernel.org&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Rob Herring &lt;robh@kernel.org&gt;
Cc: Marc Zyngier &lt;maz@kernel.org&gt;
Acked-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Frank Li &lt;Frank.Li@nxp.com&gt;
Link: https://lore.kernel.org/r/20250805133443.936955-1-lpieralisi@kernel.org
Signed-off-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
