linux-toradex.git/drivers/pci/setup-bus.c, branch v2.6.32.33

PCI: Always set prefetchable base/limit upper32 registers

2010-01-28T23:01:15+00:00

commit 59353ea30e65ab3ae181d6175e3212e1361c3787 upstream.

Prior to 1f82de10 we always initialized the upper 32bits of the
prefetchable memory window, regardless of the address range used.
Now we only touch it for a >32bit address, which means the upper32
registers remain whatever the BIOS initialized them too.

It's valid for the BIOS to set the upper32 base/limit to
0xffffffff/0x00000000, which makes us program prefetchable ranges
like 0xffffffffabc00000 - 0x00000000abc00000

Revert the chunk of 1f82de10 that made this conditional so we always
write the upper32 registers and remove now unused pref_mem64 variable.

Signed-off-by: Alex Williamson 
Signed-off-by: Jesse Barnes 
Signed-off-by: Rafael J. Wysocki 
Signed-off-by: Greg Kroah-Hartman

Revert "PCI: get larger bridge ranges when space is available"

2009-10-27T16:39:18+00:00

This reverts commit 308cf8e13f42f476dfd6552aeff58fdc0788e566.  This
patch had trouble with transparent bridges, among other things.  A more
readable and correct version should land in 2.6.33.

Signed-off-by: Jesse Barnes

PCI: get larger bridge ranges when space is available

2009-10-07T16:28:18+00:00

Found one system:
[   71.120590] pci 0000:40:05.0: scanning behind bridge, config 4f4a40, pass 0
[   71.138283] PCI: Scanning bus 0000:4a
[   71.140341] pci 0000:4a:00.0: found [15b3:6278] class 000c06 header type 00
[   71.157173] pci 0000:4a:00.0: reg 10 64bit mmio: [0x000000-0x0fffff]
[   71.161697] pci 0000:4a:00.0: reg 18 64bit mmio pref: [0x000000-0x7fffff]
[   71.179403] pci 0000:4a:00.0: reg 20 64bit mmio pref: [0x000000-0xfffffff]
[   71.185366] pci 0000:4a:00.0: calling quirk_resource_alignment+0x0/0x1dd
[   71.200846] pci 0000:4a:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'
[   71.219623] PCI: Fixups for bus 0000:4a
[   71.222194] pci 0000:40:05.0: bridge 32bit mmio: [0xcf000000-0xcf0fffff]
[   71.238662] pci 0000:40:05.0: bridge 64bit mmio pref: [0xcd800000-0xcdffffff]
[   71.255793] PCI: Bus scan for 0000:4a returning with max=4a

Device needs a big pref mmio, but BIOS doesn't allocate mmio to it aside
from a small MMIO range.  Later, the kernel will not allocate resources to
that to the device:
[   99.574030] pci 0000:4a:00.0: BAR 4: can't allocate mem resource [0xd0000000-0xcdffffff]
[   99.580102] pci 0000:4a:00.0: BAR 2: got res [0xcd800000-0xcdffffff] bus [0xcd800000-0xcdffffff] flags 0x12120c
[   99.602307] pci 0000:4a:00.0: BAR 2: moved to bus [0xcd800000-0xcdffffff] flags 0x12120c
[   99.615991] pci 0000:4a:00.0: BAR 0: got res [0xcf000000-0xcf0fffff] bus [0xcf000000-0xcf0fffff] flags 0x120204
[   99.634499] pci 0000:4a:00.0: BAR 0: moved to bus [0xcf000000-0xcf0fffff] flags 0x120204
[   99.654318] pci 0000:40:05.0: PCI bridge, secondary bus 0000:4a
[   99.658766] pci 0000:40:05.0:   IO window: disabled
[   99.675478] pci 0000:40:05.0:   MEM window: 0xcf000000-0xcf0fffff
[   99.681663] pci 0000:40:05.0:   PREFETCH window: 0x000000cd800000-0x000000cdffffff

So try to get a big range in the pci bridge if there is no child using
that range.  With the patch we get:
[   99.104525] pci 0000:4a:00.0: BAR 4: got res [0xfc080000000-0xfc08fffffff] bus [0xfc080000000-0xfc08fffffff] flags 0x12120c
[   99.123624] pci 0000:4a:00.0: BAR 4: moved to bus [0xfc080000000-0xfc08fffffff] flags 0x12120c
[   99.131977] pci 0000:4a:00.0: BAR 2: got res [0xfc090000000-0xfc0907fffff] bus [0xfc090000000-0xfc0907fffff] flags 0x12120c
[   99.149788] pci 0000:4a:00.0: BAR 2: moved to bus [0xfc090000000-0xfc0907fffff] flags 0x12120c
[   99.169248] pci 0000:4a:00.0: BAR 0: got res [0xc0200000-0xc02fffff] bus [0xc0200000-0xc02fffff] flags 0x120204
[   99.189508] pci 0000:4a:00.0: BAR 0: moved to bus [0xc0200000-0xc02fffff] flags 0x120204
[   99.206402] pci 0000:40:05.0: PCI bridge, secondary bus 0000:4a
[   99.210637] pci 0000:40:05.0:   IO window: disabled
[   99.224856] pci 0000:40:05.0:   MEM window: 0xc0200000-0xc03fffff
[   99.230019] pci 0000:40:05.0:   PREFETCH window: 0x000fc080000000-0x000fc097ffffff

Signed-off-by: Yinghai Lu 
Signed-off-by: Jesse Barnes

PCI: pcie: Ensure hotplug ports have a minimum number of resources

2009-09-09T21:10:24+00:00

In general a BIOS may goof or we may hotplug in a hotplug controller.
In either case the kernel needs to reserve resources for plugging
in more devices in the future instead of creating a minimal resource
assignment.

We already do this for cardbus bridges I am just adding a variant
for pcie bridges.

v2: Make testing for pcie hotplug bridges based on a flag.

    So far we only set the flag for pcie but a header_quirk
    could easily be added for the non-standard pci hotplug
    bridges.

Signed-off-by: Eric W. Biederman 
Signed-off-by: Jesse Barnes

PCI SR-IOV: correct broken resource alignment calculations

2009-08-30T15:37:25+00:00

An SR-IOV capable device includes an SR-IOV PCIe capability which
describes the Virtual Function (VF) BAR requirements.  A typical SR-IOV
device can support multiple VFs whose BARs must be in a contiguous region,
effectively an array of VF BARs.  The BAR reports the size requirement
for a single VF.  We calculate the full range needed by simply multiplying
the VF BAR size with the number of possible VFs and create a resource
spanning the full range.

This all seems sane enough except it artificially inflates the alignment
requirement for the VF BAR.  The VF BAR need only be aligned to the size
of a single BAR not the contiguous range of VF BARs.  This can cause us
to fail to allocate resources for the BAR despite the fact that we
actually have enough space.

This patch adds a thin PCI specific layer over the generic
resource_alignment() function which is aware of the special nature of
VF BARs and does sorting and allocation based on the smaller alignment
requirement.

I recognize that while resource_alignment is generic, it's basically a
PCI helper.  An alternative to this patch is to add PCI VF BAR specific
information to struct resource.  I opted for the extra layer rather than
adding such PCI specific information to struct resource.  This does
have the slight downside that we don't cache the BAR size and re-read
for each alignment query (happens a small handful of times during boot
for each VF BAR).

Signed-off-by: Chris Wright 
Cc: Ivan Kokshaysky 
Cc: Linus Torvalds 
Cc: Matthew Wilcox 
Cc: Yu Zhao 
Cc: stable@kernel.org
Signed-off-by: Jesse Barnes

PCI: improve resource allocation under transparent bridges

2009-06-11T19:04:07+00:00

We could run out of space under under 4g, but devices under transparent
bridges can use 64bit resources, so keep trying on the parent bus until
we hit a non-transparent bridge.

Impact: better support for assigning unassigned resources

Reviewed-by: Ivan Kokshaysky 
Signed-off-by: Yinghai Lu 
Signed-off-by: Jesse Barnes

PCI/x86: don't assume prefetchable ranges are 64bit

2009-06-11T19:04:06+00:00

We should not assign 64bit ranges to PCI devices that only take 32bit
prefetchable addresses.

Try to set IORESOURCE_MEM_64 in 64bit resource of pci_device/pci_bridge
and make the bus resource only have that bit set when all devices under
it support 64bit prefetchable memory.  Use that flag to allocate
resources from that range.

Reported-by: Yannick 
Reviewed-by: Ivan Kokshaysky 
Signed-off-by: Yinghai Lu 
Signed-off-by: Jesse Barnes

PCI: cleanup debug output resources

2009-04-22T21:49:25+00:00

Remove outputs for 0 sized resources and indicate prefetchability.

Signed-off-by: Yinghai Lu 
Signed-off-by: Jesse Barnes

PCI: Setup disabled bridges even if buses are added

2009-04-06T18:25:06+00:00

This patch sets up disabled bridges even if buses have already been
added.

pci_assign_unassigned_resources is called after buses are added.
pci_assign_unassigned_resources calls pci_bus_assign_resources.
pci_bus_assign_resources calls pci_setup_bridge to configure BARs of
bridges.

Currently pci_setup_bridge returns immediately if the bus have already
been added. So pci_assign_unassigned_resources can't configure BARs of
bridges that were added in a disabled state; this patch fixes the issue.

On logical hot-add, we need to prevent the kernel from re-initializing
bridges that have already been initialized. To achieve this,
pci_setup_bridge returns immediately if the bridge have already been
enabled.

We don't need to check whether the specified bus is a root bus or not.
pci_setup_bridge is not called on a root bus, because a root bus does
not have a bridge.

The patch adds a new helper function, pci_is_enabled. I made the
function name similar to pci_is_managed. The codes which use
enable_cnt directly are changed to use pci_is_enabled.

Acked-by: Alex Chiang 
Signed-off-by: Yuji Shimada 
Signed-off-by: Jesse Barnes

PCI: do not initialize bridges more than once

2009-03-20T21:57:32+00:00

In preparation for PCI core hotplug, we need to ensure that we do
not attempt to re-initialize bridges that have already been initialized.

We only need to worry about non-root buses, since we will not allow
root bus removal.

Reported-by: Kenji Kaneshige 
Signed-off-by: Alex Chiang 
Signed-off-by: Jesse Barnes