linux-toradex.git/drivers/pci, branch v3.12.29

PCI: Configure ASPM when enabling device

2014-09-03T19:31:30+00:00

commit 1f6ae47ecff7f23da73417e068018b311f3b5583 upstream.

We can't do ASPM configuration at enumeration-time because enabling it
makes some defective hardware unresponsive, even if ASPM is disabled later
(see 41cd766b0659 ("PCI: Don't enable aspm before drivers have had a chance
to veto it").  Therefore, we have to do it after a driver claims the
device.

We previously configured ASPM in pci_set_power_state(), but that's not a
very good place because it's not really related to setting the PCI device
power state, and doing it there means:

  - We incorrectly skipped ASPM config when setting a device that's
    already in D0 to D0.

  - We unnecessarily configured ASPM when setting a device to a low-power
    state (the ASPM feature only applies when the device is in D0).

  - We unnecessarily configured ASPM when called from a .resume() method
    (ASPM configuration needs to be restored during resume, but
    pci_restore_pcie_state() should already do this).

Move ASPM configuration from pci_set_power_state() to
do_pci_enable_device() so we do it when a driver enables a device.

[bhelgaas: changelog]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=79621
Fixes: db288c9c5f9d ("PCI / PM: restore the original behavior of pci_set_power_state()")
Suggested-by: Bjorn Helgaas 
Signed-off-by: Vidya Sagar 
Signed-off-by: Bjorn Helgaas 
Signed-off-by: Jiri Slaby

PCI: rphahp: Fix endianess issues

2014-08-26T12:12:22+00:00

commit 761ce53330a4f02c58768631027d1c1dd0d538f7 upstream.

Numerical values stored in the device tree are encoded in Big Endian and
should be byte swapped when running in Little Endian.

The RPA hotplug module should convert those values as well.

Note that in rpaphp_get_drc_props(), the comparison between indexes[i+1]
and *index is done using the BE values (whatever is the current endianess).
This doesn't matter since we are checking for equality here.  This way only
the returned value is byte swapped.

RPA also made RTAS calls which implies BE values to be used.  According to
the patch done in RTAS (http://patchwork.ozlabs.org/patch/336865), no
additional conversion is required in RPA.

Signed-off-by: Laurent Dufour 
Signed-off-by: Bjorn Helgaas 

Signed-off-by: Jiri Slaby

PCI: Fix incorrect vgaarb conditional in WARN_ON()

2014-07-17T11:43:15+00:00

commit 67ebd8140dc8923c65451fa0f6a8eee003c4dcd3 upstream.

3448a19da479 "vgaarb: use bridges to control VGA routing where possible"
added the "flags & PCI_VGA_STATE_CHANGE_DECODES" condition to an existing
WARN_ON(), but used bitwise AND (&) instead of logical AND (&&), so the
condition is never true.  Replace with logical AND.

Found by Coverity (CID 142811).

Fixes: 3448a19da479 "vgaarb: use bridges to control VGA routing where possible"
Signed-off-by: Bjorn Helgaas 
Acked-by: Yinghai Lu 
Acked-by: David Airlie 
Signed-off-by: Jiri Slaby

PCI: Add new ID for Intel GPU "spurious interrupt" quirk

2014-07-17T11:43:15+00:00

commit 7c82126a94e69bbbac586f0249e7ef11e681246c upstream.

After a CPU upgrade while keeping the same mainboard, we faced "spurious
interrupt" problems again.

It turned out that the new CPU also featured a new GPU with a different PCI
ID.

Add this PCI ID to the quirk table.  Probably all other Intel GPU PCI IDs
are affected, too, but I don't want to add them without a test system.

See f67fd55fa96f ("PCI: Add quirk for still enabled interrupts on Intel
Sandy Bridge GPUs") for some history.

[bhelgaas: add f67fd55fa96f reference, stable tag]
Signed-off-by: Thomas Jarosch 
Signed-off-by: Bjorn Helgaas 
Signed-off-by: Jiri Slaby

PCI: shpchp: Check bridge's secondary (not primary) bus speed

2014-06-09T13:53:43+00:00

commit 93fa9d32670f5592c8e56abc9928fc194e1e72fc upstream.

When a new device is added below a hotplug bridge, the bridge's secondary
bus speed and the device's bus speed must match.  The shpchp driver
previously checked the bridge's *primary* bus speed, not the secondary bus
speed.

This caused hot-add errors like:

  shpchp 0000:00:03.0: Speed of bus ff and adapter 0 mismatch

Check the secondary bus speed instead.

[bhelgaas: changelog]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=75251
Fixes: 3749c51ac6c1 ("PCI: Make current and maximum bus speeds part of the PCI core")
Signed-off-by: Marcel Apfelbaum 
Signed-off-by: Bjorn Helgaas 
Acked-by: Michael S. Tsirkin 
Signed-off-by: Jiri Slaby

PCI: mvebu: fix off-by-one in the computed size of the mbus windows

2014-06-09T13:53:38+00:00

commit b6d07e0273d3296cfbdc88145b8a00ddbefb310a upstream.

mvebu_pcie_handle_membase_change() and
mvebu_pcie_handle_iobase_change() do not correctly compute the window
size. PCI uses an inclusive start/end address pair, which requires a
+1 when converting to size.

This only worked because a bug in the mbus driver allowed it to
silently accept and round up bogus sizes.

Fix this by adding one to the computed size.

Fixes: 45361a4fe446 ('PCIe driver for Marvell Armada 370/XP systems')
Signed-off-by: Willy Tarreau 
Reviewed-By: Jason Gunthorpe 
Signed-off-by: Thomas Petazzoni 
Link: https://lkml.kernel.org/r/1397823593-1932-5-git-send-email-thomas.petazzoni@free-electrons.com
Tested-by: Neil Greatorex 
Acked-by: Bjorn Helgaas 
Signed-off-by: Jason Cooper 
Signed-off-by: Jiri Slaby

PCI: mvebu: Fix potential issue in range parsing

2014-05-15T07:55:03+00:00

commit 4f4bde1df33bde076f53325bdf2c6430cf85e1bb upstream.

The second parameter of of_read_number() is not the index, but a size.  As
it happens, in this case it may work just fine because of the conversion to
u32 and the favorable endianness on this architecture.

Fixes: 11be65472a427 ("PCI: mvebu: Adapt to the new device tree layout")
Tested-by: Thomas Petazzoni 
Signed-off-by: Jean-Jacques Hiblot 
Signed-off-by: Bjorn Helgaas 
Acked-by: Thomas Petazzoni 
Acked-by: Jason Cooper 
Signed-off-by: Jiri Slaby

PCI: designware: Fix iATU programming for cfg1, io and mem viewport

2014-05-05T12:24:35+00:00

commit 017fcdc30cdae18c0946eef1ece1f14b4c7897ba upstream.

This patch corrects iATU programming for cfg1, io and mem viewport.  Enable
ATU only after configuring it.

Signed-off-by: Mohit Kumar 
Signed-off-by: Ajay Khandelwal 
Signed-off-by: Bjorn Helgaas 
Acked-by: Jingoo Han 
Signed-off-by: Jiri Slaby

PCI: designware: Fix RC BAR to be single 64-bit non-prefetchable memory BAR

2014-05-05T12:24:35+00:00

commit dbffdd6862e67d60703f2df66c558bf448f81d6e upstream.

The Synopsys PCIe core provides one pair of 32-bit BARs (BAR 0 and BAR 1).
The BARs can be configured as follows:

  - One 64-bit BAR: BARs 0 and 1 are combined to form a single 64-bit BAR
  - Two 32-bit BARs: BARs 0 and 1 are two independent 32-bit BARs

This patch corrects 64-bit, non-prefetchable memory BAR configuration
implemented in dw driver.

Signed-off-by: Mohit Kumar 
Signed-off-by: Bjorn Helgaas 
Cc: Pratyush Anand 
Cc: Jingoo Han 
Cc: Arnd Bergmann 
Signed-off-by: Jiri Slaby

PCI: mvebu: move clock enable before register access

2014-04-13T14:33:22+00:00

commit b42285f66f871a9898a0e79e2d74bc7e7a101995 upstream.

The clock passed to PCI controller found on MVEBU SoCs may come from a
clock gate. This requires the clock to be enabled before any registers
are accessed. Therefore, move the clock enable before register iomap to
ensure it is enabled.

Signed-off-by: Sebastian Hesselbarth 
Signed-off-by: Jason Cooper 
Signed-off-by: Jiri Slaby