linux-toradex.git/drivers/pci, branch v3.2-rt10

pci: Use __wake_up_all_locked pci_unblock_user_cfg_access()

2012-01-16T19:00:11+00:00

The waitqueue is protected by the pci_lock, so we can just avoid to
lock the waitqueue lock itself. That prevents the
might_sleep()/scheduling while atomic problem on RT

Signed-off-by: Thomas Gleixner 
Cc: stable-rt@vger.kernel.org

pci: Fix hotplug of Express Module with pci bridges

2011-12-18T22:10:16+00:00

I noticed that hotplug of one setup does not work with recent change in
pci tree.

After checking the bridge conf setup, I noticed that the bridges get
assigned but do not get enabled.

The reason is the following commit, while simply ignores bridge
resources when enabling a pci device:

| commit bbef98ab0f019f1b0c25c1acdf1683c68933d41b
| Author: Ram Pai 
| Date:   Sun Nov 6 10:33:10 2011 +0800
|
|    PCI: defer enablement of SRIOV BARS
|...
|    NOTE: Note, there is subtle change in the pci_enable_device() API.  Any
|    driver that depends on SRIOV BARS to be enabled in pci_enable_device()
|    can fail.

Put back bridge resource and ROM resource checking to fix the problem.

That should fix regression like BIOS does not assign correct resource to
bridge.

Discussion can be found at:
	http://www.spinics.net/lists/linux-pci/msg12874.html

Signed-off-by: Yinghai Lu 
Acked-by: Jesse Barnes 
Signed-off-by: Linus Torvalds

PCI: Set device power state to PCI_D0 for device without native PM support

2011-12-14T16:26:42+00:00

During test of one IB card with guest VM, found that, msi is not
initialized properly.

It turns out __write_msi_msg will do nothing if device current_state is
not PCI_D0.  And, that pci device does not have pm_cap in guest VM.

There is an error in setting of power state to PCI_D0 in
pci_enable_device(), but error is not returned for this.  Following is
code flow:

pci_enable_device() -->   __pci_enable_device_flags() -->
do_pci_enable_device() -->   pci_set_power_state() -->
__pci_start_power_transition()

We have following condition inside __pci_start_power_transition():
         if (platform_pci_power_manageable(dev)) {
                 error = platform_pci_set_power_state(dev, state);
                 if (!error)
                         pci_update_current_state(dev, state);
         } else {
                 error = -ENODEV;
                 /* Fall back to PCI_D0 if native PM is not supported */
                 if (!dev->pm_cap)
                         dev->current_state = PCI_D0;
         }

Here, from platform_pci_set_power_state(), acpi_pci_set_power_state() is
getting called and that is failing with ENODEV because of following
condition:

         if (!handle || ACPI_SUCCESS(acpi_get_handle(handle, "_EJ0",&tmp)))
                 return -ENODEV;

Because of that, pci_update_current_state() is not getting called.

With this patch, if device power state can not be set via
platform_pci_set_power_state and that device does not have native pm
support, then PCI device power state will be set to PCI_D0.

-v2: This also reverts 47e9037ac16637cd7f12b8790ea7ce6680e42168, as it's
     not needed after this change.

Acked-by: "Rafael J. Wysocki" 
Signed-off-by: Ajaykumar Hotchandani
Signed-off-by: Yinghai Lu
Signed-off-by: Jesse Barnes

PCI hotplug: Always allow acpiphp to handle non-PCIe bridges

2011-12-13T18:41:23+00:00

Commit 0d52f54e2ef64c189dedc332e680b2eb4a34590a (PCI / ACPI: Make
acpiphp ignore root bridges using PCIe native hotplug) added code
that made the acpiphp driver completely ignore PCIe root complexes
for which the kernel had been granted control of the native PCIe
hotplug feature by the BIOS through _OSC.  Unfortunately, however,
this was a mistake, because on some systems there were PCI bridges
supporting PCI (non-PCIe) hotplug under such root complexes and
those bridges should have been handled by acpiphp.

For this reason, revert the changes made by the commit mentioned
above and make register_slot() in drivers/pci/hotplug/acpiphp_glue.c
avoid registering hotplug slots for PCIe ports that belong to
root complexes with native PCIe hotplug enabled (which means that
the BIOS has granted the kernel control of this feature for the
given root complex).  This is reported to address the original
issue fixed by commit 0d52f54e2ef64c189dedc332e680b2eb4a34590a and
to work on the system where that commit broke things.

Signed-off-by: Rafael J. Wysocki 
Signed-off-by: Jesse Barnes

PCI: fix ats compile failure

2011-12-05T18:31:25+00:00

I get this compile failure on parisc:

drivers/pci/ats.c: In function 'ats_alloc_one':
drivers/pci/ats.c:29: error: implicit declaration of function 'kzalloc'
drivers/pci/ats.c:29: warning: assignment makes pointer from integer without a cast
drivers/pci/ats.c: In function 'ats_free_one':
drivers/pci/ats.c:45: error: implicit declaration of function 'kfree'

Because ats.c is missing linux/slab.h as an include.  This patch fixes it

Signed-off-by: James Bottomley 
Signed-off-by: Jesse Barnes

PCI: defer enablement of SRIOV BARS

2011-12-05T18:30:22+00:00

All the PCI BARs of a device are enabled when the device is enabled
using pci_enable_device().  This unnecessarily enables SRIOV BARs of the
device.

On some platforms, which do not support SRIOV as yet, the
pci_enable_device() fails to enable the device if its SRIOV BARs are not
allocated resources correctly.

The following patch fixes the above problem. The SRIOV BARs are now
enabled when IOV capability of the device is enabled in sriov_enable().

NOTE: Note, there is subtle change in the pci_enable_device() API.  Any
driver that depends on SRIOV BARS to be enabled in pci_enable_device()
can fail.

The patch has been touch tested on power and x86 platform.

Tested-by: Michael Wang 
Signed-off-by: Ram Pai 
Signed-off-by: Jesse Barnes

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci

2011-11-23T22:58:46+00:00

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci:
  PCI hotplug: shpchp: don't blindly claim non-AMD 0x7450 device IDs
  PCI: pciehp: wait 100 ms after Link Training check
  PCI: pciehp: wait 1000 ms before Link Training check
  PCI: pciehp: Retrieve link speed after link is trained
  PCI: Let PCI_PRI depend on PCI
  PCI: Fix compile errors with PCI_ATS and !PCI_IOV
  PCI / ACPI: Make acpiphp ignore root bridges using PCIe native hotplug

PCI hotplug: shpchp: don't blindly claim non-AMD 0x7450 device IDs

2011-11-14T17:43:14+00:00

Previously we claimed device ID 0x7450, regardless of the vendor, which is
clearly wrong.  Now we'll claim that device ID only for AMD.

I suspect this was just a typo in the original code, but it's possible this
change will break shpchp on non-7450 AMD bridges.  If so, we'll have to fix
them as we find them.

Reference: http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=638863
Reported-by: Ralf Jung 
Cc: Joerg Roedel 
Signed-off-by: Bjorn Helgaas 
Signed-off-by: Jesse Barnes

PCI: pciehp: wait 100 ms after Link Training check

2011-11-11T17:31:43+00:00

If the port supports Link speeds greater than 5.0 GT/s, we must wait
for 100 ms after Link training completes before sending configuration
request.

Acked-by: Yinghai Lu 
Tested-by: Yinghai Lu 
Signed-off-by: Kenji Kaneshige 
Signed-off-by: Jesse Barnes

PCI: pciehp: wait 1000 ms before Link Training check

2011-11-11T17:31:34+00:00

We need to wait for 1000 ms after Data Link Layer Link Active (DLLLA)
bit reads 1b before sending configuration request. Currently pciehp
does this wait after checking Link Training (LT) bit. But we need it
before checking LT bit because LT is still set even after DLLLA bit is
set on some platforms.

Acked-by: Yinghai Lu 
Tested-by: Yinghai Lu 
Signed-off-by: Kenji Kaneshige 
Signed-off-by: Jesse Barnes