linux-toradex.git/drivers/perf, branch v4.13-rc4 Linux kernel for Apalis and Colibri modules drivers/perf: arm_pmu: Request PMU SPIs with IRQF_PER_CPU 2017-07-27T12:43:22+00:00 Will Deacon will.deacon@arm.com 2017-07-25T15:30:34+00:00 a3287c41ff405025bc57b165a0f6cd698bbbc1be Since the PMU register interface is banked per CPU, CPU PMU interrrupts cannot be handled by a CPU other than the one with the PMU asserting the interrupt. This means that migrating PMU SPIs, as we do during a CPU hotplug operation doesn't make any sense and can lead to the IRQ being disabled entirely if we route a spurious IRQ to the new affinity target. This has been observed in practice on AMD Seattle, where CPUs on the non-boot cluster appear to take a spurious PMU IRQ when coming online, which is routed to CPU0 where it cannot be handled. This patch passes IRQF_PERCPU for PMU SPIs and forcefully sets their affinity prior to requesting them, ensuring that they cannot be migrated during hotplug events. This interacts badly with the DB8500 erratum workaround that ping-pongs the interrupt affinity from the handler, so we avoid passing IRQF_PERCPU in that case by allowing the IRQ flags to be overridden in the platdata. Fixes: 3cf7ee98b848 ("drivers/perf: arm_pmu: move irq request/free into probe") Cc: Mark Rutland <mark.rutland@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> 
Since the PMU register interface is banked per CPU, CPU PMU interrrupts
cannot be handled by a CPU other than the one with the PMU asserting the
interrupt. This means that migrating PMU SPIs, as we do during a CPU
hotplug operation doesn't make any sense and can lead to the IRQ being
disabled entirely if we route a spurious IRQ to the new affinity target.

This has been observed in practice on AMD Seattle, where CPUs on the
non-boot cluster appear to take a spurious PMU IRQ when coming online,
which is routed to CPU0 where it cannot be handled.

This patch passes IRQF_PERCPU for PMU SPIs and forcefully sets their
affinity prior to requesting them, ensuring that they cannot
be migrated during hotplug events. This interacts badly with the DB8500
erratum workaround that ping-pongs the interrupt affinity from the handler,
so we avoid passing IRQF_PERCPU in that case by allowing the IRQ flags
to be overridden in the platdata.

Fixes: 3cf7ee98b848 ("drivers/perf: arm_pmu: move irq request/free into probe")
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
perf: qcom_l2: fix column exclusion check 2017-07-26T08:27:43+00:00 Neil Leeder nleeder@codeaurora.org 2017-07-24T21:17:02+00:00 6c17c1c3099d7367e67d51290884846dfeecf7bf The check for column exclusion did not verify that the event being checked was an L2 event, and not a software event. Software events should not be checked for column exclusion. This resulted in a group with both software and L2 events sometimes incorrectly rejecting the L2 event for column exclusion and not counting it. Add a check for PMU type before applying column exclusion logic. Fixes: 21bdbb7102edeaeb ("perf: add qcom l2 cache perf events driver") Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Neil Leeder <nleeder@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com> 
The check for column exclusion did not verify that the event being
checked was an L2 event, and not a software event.
Software events should not be checked for column exclusion.
This resulted in a group with both software and L2 events sometimes
incorrectly rejecting the L2 event for column exclusion and
not counting it.

Add a check for PMU type before applying column exclusion logic.

Fixes: 21bdbb7102edeaeb ("perf: add qcom l2 cache perf events driver")
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
perf: Convert to using %pOF instead of full_name 2017-07-20T09:28:41+00:00 Rob Herring robh@kernel.org 2017-07-18T21:43:22+00:00 5f4216f49ba19a6ba9e1f286e7de69b70991742b Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Will Deacon <will.deacon@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Will Deacon <will.deacon@arm.com> 
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Will Deacon <will.deacon@arm.com>
Merge branch 'aarch64/for-next/ras-apei' into aarch64/for-next/core 2017-06-26T09:54:27+00:00 Will Deacon will.deacon@arm.com 2017-06-26T09:54:27+00:00 3edb1dd13ce6f6480c1f2bffc47a49cf959fa9cb Merge in arm64 ACPI RAS support (APEI/GHES) from Tyler Baicar. 
Merge in arm64 ACPI RAS support (APEI/GHES) from Tyler Baicar.
perf: xgene: Add support for SoC PMU version 3 2017-06-22T19:16:34+00:00 Hoan Tran hotran@apm.com 2017-06-22T18:26:05+00:00 c0f7f7acdecdd7cf9a19c0af5c3dc649e1b934f7 This patch adds support for SoC-wide (AKA uncore) Performance Monitoring Unit version 3. It can support up to - 2 IOB PMU instances - 8 L3C PMU instances - 2 MCB PMU instances - 8 MCU PMU instances and these PMUs support 64 bit counter Signed-off-by: Hoan Tran <hotran@apm.com> [Mark: stop counters in _xgene_pmu_isr()] Signed-off-by: Mark Rutland <mark.rutland@arm.com> [will: make xgene_pmu_v3_ops static] Signed-off-by: Will Deacon <will.deacon@arm.com> 
This patch adds support for SoC-wide (AKA uncore) Performance Monitoring
Unit version 3.

It can support up to
 - 2 IOB PMU instances
 - 8 L3C PMU instances
 - 2 MCB PMU instances
 - 8 MCU PMU instances
and these PMUs support 64 bit counter

Signed-off-by: Hoan Tran <hotran@apm.com>
[Mark: stop counters in _xgene_pmu_isr()]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
[will: make xgene_pmu_v3_ops static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
perf: xgene: Move PMU leaf functions into function pointer structure 2017-06-22T19:16:18+00:00 Hoan Tran hotran@apm.com 2017-06-22T18:26:04+00:00 e35e0a04a9965bcb4fffe4375baaecd408ad2357 This patch moves PMU leaf functions into a function pointer structure. It helps code maintain and expasion easier. Signed-off-by: Hoan Tran <hotran@apm.com> [Mark: remove redundant cast] Signed-off-by: Mark Rutland <mark.rutland@arm.com> [will: make xgene_pmu_ops static] Signed-off-by: Will Deacon <will.deacon@arm.com> 
This patch moves PMU leaf functions into a function pointer structure.
It helps code maintain and expasion easier.

Signed-off-by: Hoan Tran <hotran@apm.com>
[Mark: remove redundant cast]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
[will: make xgene_pmu_ops static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
perf: xgene: Parse PMU subnode from the match table 2017-06-22T18:30:09+00:00 Hoan Tran hotran@apm.com 2017-06-22T18:26:03+00:00 838955e2a3c010aff9089fd705ae2cd5638cdee8 This patch parses PMU Subnode from a match table. Signed-off-by: Hoan Tran <hotran@apm.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> 
This patch parses PMU Subnode from a match table.

Signed-off-by: Hoan Tran <hotran@apm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
drivers/perf: commonise PERF_EVENTS dependency 2017-06-15T10:10:33+00:00 Mark Rutland mark.rutland@arm.com 2017-06-13T12:45:51+00:00 bddb9b68d3fb0dfbd75715bce6160c40d4dae233 All PMU drivers are going to depend on PERF_EVENTS, so let's make this dependency common and simplify the individual Kconfig entries. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> 
All PMU drivers are going to depend on PERF_EVENTS, so let's make this
dependency common and simplify the individual Kconfig entries.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
drivers/perf: arm_pmu_acpi: avoid perf IRQ init when guest PMU is off 2017-05-30T11:40:03+00:00 Wei Huang wei@redhat.com 2017-05-30T10:56:22+00:00 477c50e8dc1c7b5004e099b8b74ca8b70be2f4fd We saw perf IRQ init failures when running Linux kernel in an ACPI guest without PMU (i.e. pmu=off). This is because perf IRQ is not present when pmu=off, but arm_pmu_acpi still tries to register or unregister GSI. This patch addresses the problem by checking gicc->performance_interrupt. If it is 0, which is the value set by qemu when pmu=off, we skip the IRQ register/unregister process. [ 4.069470] bc00: 0000000000040b00 ffff0000089db190 [ 4.070267] [<ffff000008134f80>] enable_percpu_irq+0xdc/0xe4 [ 4.071192] [<ffff000008667cc4>] arm_perf_starting_cpu+0x108/0x10c [ 4.072200] [<ffff0000080cbdd4>] cpuhp_invoke_callback+0x14c/0x4ac [ 4.073210] [<ffff0000080ccd3c>] cpuhp_thread_fun+0xd4/0x11c [ 4.074132] [<ffff0000080f1394>] smpboot_thread_fn+0x1b4/0x1c4 [ 4.075081] [<ffff0000080ec90c>] kthread+0x10c/0x138 [ 4.075921] [<ffff0000080833c0>] ret_from_fork+0x10/0x50 [ 4.076947] genirq: Setting trigger mode 4 for irq 43 failed (gic_set_type+0x0/0x74) Signed-off-by: Wei Huang <wei@redhat.com> [will: add comment justifying deviation from ACPI spec, removed redundant hunk] Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 
We saw perf IRQ init failures when running Linux kernel in an ACPI
guest without PMU (i.e. pmu=off). This is because perf IRQ is not
present when pmu=off, but arm_pmu_acpi still tries to register
or unregister GSI. This patch addresses the problem by checking
gicc->performance_interrupt. If it is 0, which is the value set
by qemu when pmu=off, we skip the IRQ register/unregister process.

[    4.069470] bc00: 0000000000040b00 ffff0000089db190
[    4.070267] [<ffff000008134f80>] enable_percpu_irq+0xdc/0xe4
[    4.071192] [<ffff000008667cc4>] arm_perf_starting_cpu+0x108/0x10c
[    4.072200] [<ffff0000080cbdd4>] cpuhp_invoke_callback+0x14c/0x4ac
[    4.073210] [<ffff0000080ccd3c>] cpuhp_thread_fun+0xd4/0x11c
[    4.074132] [<ffff0000080f1394>] smpboot_thread_fn+0x1b4/0x1c4
[    4.075081] [<ffff0000080ec90c>] kthread+0x10c/0x138
[    4.075921] [<ffff0000080833c0>] ret_from_fork+0x10/0x50
[    4.076947] genirq: Setting trigger mode 4 for irq 43 failed
(gic_set_type+0x0/0x74)

Signed-off-by: Wei Huang <wei@redhat.com>
[will: add comment justifying deviation from ACPI spec, removed redundant hunk]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
drivers/perf: arm_pmu: add ACPI framework 2017-04-11T15:29:54+00:00 Mark Rutland mark.rutland@arm.com 2017-04-11T08:39:55+00:00 45736a72fb79b204c1fbdb08a1e1a2aa52c7281a This patch adds framework code to handle parsing PMU data out of the MADT, sanity checking this, and managing the association of CPUs (and their interrupts) with appropriate logical PMUs. For the time being, we expect that only one PMU driver (PMUv3) will make use of this, and we simply pass in a single probe function. This is based on an earlier patch from Jeremy Linton. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Jeremy Linton <jeremy.linton@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> 
This patch adds framework code to handle parsing PMU data out of the
MADT, sanity checking this, and managing the association of CPUs (and
their interrupts) with appropriate logical PMUs.

For the time being, we expect that only one PMU driver (PMUv3) will make
use of this, and we simply pass in a single probe function.

This is based on an earlier patch from Jeremy Linton.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>