linux-toradex.git/drivers/phy/cadence, branch master

phy: cadence-torrent: Add PCIe + XAUI multilink configuration for 100MHz refclk

2026-01-14T09:33:09+00:00

Add register sequences for PCIe + XAUI multilink configuration for
100MHz reference clock.

The register sequences are fetched from a table by indexing entries based
on unique 'keys' generated by the Bitwise OR defined below:
	REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE

As of now, LINK_TYPE is a 3-bit value corresponding to the PHY type.
With the introduction of TYPE_XAUI, we need a 4-bit value to represent
the LINK_TYPE as TYPE_XAUI has the numerical value 8. Hence, extend the
LINKx_MASK macros to 4-bit masks. While at it, extend REFCLKx_MASK macros
as well to 4-bit masks to support reference clock frequencies that will be
added in the future.

Adjust the 'LINKx_SHIFT' and the 'REFCLKx_SHIFT' macros to account for
the aforementioned changes made to the masks.

Signed-off-by: Swapnil Jakhade 
[s-vadapalli: elaborated on changes made to macros in the commit message]
Signed-off-by: Siddharth Vadapalli 
Reviewed-by: Andrew Lunn 
Link: https://patch.msgid.link/20260112054636.108027-3-s-vadapalli@ti.com
Signed-off-by: Vinod Koul

phy: cadence-torrent: restore parent clock for refclk during resume

2025-12-23T17:41:04+00:00

While suspend and resume, parent clock config for refclk was getting lost.
So save and restore it in suspend and resume operations.

Reviewed-by: Neil Armstrong 
Signed-off-by: Thomas Richard (TI.com) 
Link: https://patch.msgid.link/20251216-phy-cadence-torrent-resume-restore-refclk-parent-v3-1-8a7ed84b47e3@bootlin.com
Signed-off-by: Vinod Koul

phy: cadence: cdns-dphy: Enable lower resolutions in dphy

2025-09-10T15:52:22+00:00

Enable support for data lane rates between 80-160 Mbps cdns dphy
as mentioned in TRM [0] by setting the pll_opdiv field to 16.
This change enables lower resolutions like 640x480 at 60Hz.

[0]: https://www.ti.com/lit/zip/spruil1
(Table 12-552. DPHY_TX_PLL_CTRL Register Field Descriptions)

Reviewed-by: Udit Kumar 
Reviewed-by: Devarsh Thakkar 
Signed-off-by: Harikrishna Shenoy 
Link: https://lore.kernel.org/r/20250807052002.717807-1-h-shenoy@ti.com
Signed-off-by: Vinod Koul

phy: cadence: cdns-dphy: Update calibration wait time for startup state machine

2025-09-10T15:12:33+00:00

Do read-modify-write so that we re-use the characterized reset value as
specified in TRM [1] to program calibration wait time which defines number
of cycles to wait for after startup state machine is in bandgap enable
state.

This fixes PLL lock timeout error faced while using RPi DSI Panel on TI's
AM62L and J721E SoC since earlier calibration wait time was getting
overwritten to zero value thus failing the PLL to lockup and causing
timeout.

[1] AM62P TRM (Section 14.8.6.3.2.1.1 DPHY_TX_DPHYTX_CMN0_CMN_DIG_TBIT2):
Link: https://www.ti.com/lit/pdf/spruj83

Cc: stable@vger.kernel.org
Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support")
Signed-off-by: Devarsh Thakkar 
Tested-by: Harikrishna Shenoy 
Reviewed-by: Tomi Valkeinen 
Link: https://lore.kernel.org/r/20250704125915.1224738-3-devarsht@ti.com
Signed-off-by: Vinod Koul

phy: cadence: cdns-dphy: Fix PLL lock and O_CMN_READY polling

2025-09-10T15:12:33+00:00

PLL lockup and O_CMN_READY assertion can only happen after common state
machine gets enabled by programming DPHY_CMN_SSM register, but driver was
polling them before the common state machine was enabled which is
incorrect.  This is as per the DPHY initialization sequence as mentioned in
J721E TRM [1] at section "12.7.2.4.1.2.1 Start-up Sequence Timing Diagram".
It shows O_CMN_READY polling at the end after common configuration pin
setup where the common configuration pin setup step enables state machine
as referenced in "Table 12-1533. Common Configuration-Related Setup
mentions state machine"

To fix this :
- Add new function callbacks for polling on PLL lock and O_CMN_READY
  assertion.
- As state machine and clocks get enabled in power_on callback only, move
  the clock related programming part from configure callback to power_on
callback and poll for the PLL lockup and O_CMN_READY assertion after state
machine gets enabled.
- The configure callback only saves the PLL configuration received from the
  client driver which will be applied later on in power_on callback.
- Add checks to ensure configure is called before power_on and state
  machine is in disabled state before power_on callback is called.
- Disable state machine in power_off so that client driver can re-configure
  the PLL by following up a power_off, configure, power_on sequence.

[1]: https://www.ti.com/lit/zip/spruil1

Cc: stable@vger.kernel.org
Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support")
Signed-off-by: Devarsh Thakkar 
Tested-by: Harikrishna Shenoy 
Reviewed-by: Tomi Valkeinen 
Link: https://lore.kernel.org/r/20250704125915.1224738-2-devarsht@ti.com
Signed-off-by: Vinod Koul

phy: cadence: Sierra: drop unused module alias

2025-08-13T06:49:24+00:00

The driver has never supported anything but OF probe so drop the unused
platform module alias.

Signed-off-by: Johan Hovold 
Reviewed-by: Neil Armstrong 
Link: https://lore.kernel.org/r/20250724154823.15998-4-johan@kernel.org
Signed-off-by: Vinod Koul

phy: cadence: cdns-dphy-rx: Add runtime PM support

2025-08-13T06:49:24+00:00

Enable runtime power management for the device. The PHY framework
handles calling pm_runtime_(get|put)_sync when powering on/off this
device.

Signed-off-by: Jai Luthra 
Link: https://lore.kernel.org/r/20250224-cdns_phy_pm-v1-1-0fe2c544cc87@ideasonboard.com
Signed-off-by: Vinod Koul

phy: cdns-dphy: Remove leftover code

2025-08-13T06:49:24+00:00

The code in cdns-dphy has probably been part of a DSI driver in the
past. Remove DSI defines and variables which are not used or do not
actually do anything. Also rename cdns_dsi_get_dphy_pll_cfg() to
cdns_dphy_get_pll_cfg(), i.e. drop the "dsi", as it's not relevant here.

Reviewed-by: Aradhya Bhatia 
Tested-by: Parth Pancholi 
Acked-by: Vinod Koul 
Tested-by: Jayesh Choudhary 
Reviewed-by: Devarsh Thakkar 
Signed-off-by: Tomi Valkeinen 
Link: https://lore.kernel.org/r/20250723-cdns-dphy-hs-clk-rate-fix-v1-2-d4539d44cbe7@ideasonboard.com
Signed-off-by: Vinod Koul

phy: cdns-dphy: Store hs_clk_rate and return it

2025-08-13T06:49:24+00:00

The DPHY driver does not return the actual hs_clk_rate, so the DSI
driver has no idea what clock was actually achieved. Set the realized
hs_clk_rate to the opts struct, so that the DSI driver gets it back.

Reviewed-by: Aradhya Bhatia 
Tested-by: Parth Pancholi 
Tested-by: Jayesh Choudhary 
Acked-by: Vinod Koul 
Reviewed-by: Devarsh Thakkar 
Signed-off-by: Tomi Valkeinen 
Link: https://lore.kernel.org/r/20250723-cdns-dphy-hs-clk-rate-fix-v1-1-d4539d44cbe7@ideasonboard.com
Signed-off-by: Vinod Koul

phy: cadence-torrent: Add PCIe multilink + USB with same SSC register config for 100 MHz refclk

2025-06-16T17:07:19+00:00

Add register sequences and support for PCIe multilink + USB configuration
for 100MHz reference clock. The same SSC is used for both PCIe and USB.

Signed-off-by: Swapnil Jakhade 
Co-developed-by: Siddharth Vadapalli 
Signed-off-by: Siddharth Vadapalli 
Reviewed-by: Roger Quadros 
Link: https://lore.kernel.org/r/20250616064705.3225758-3-s-vadapalli@ti.com
Signed-off-by: Vinod Koul