linux-toradex.git/drivers/phy/cadence, branch v5.16 Linux kernel for Apalis and Colibri modules phy: cadence-torrent: Add support to output received reference clock 2021-10-26T11:06:23+00:00 Swapnil Jakhade sjakhade@cadence.com 2021-09-22T12:37:35+00:00 785a4e688cd29adfe9a5f7a7d20f877f5b8ac4fa Add support to output received reference clock. Model the received reference clock as an alternate parent of reference clock driver clock. When received refclk is selected to output on cmn_refclk_p/m, this is the internal reference clock driven on the pma_cmn_refclk_int. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210922123735.21927-5-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add support to output received reference clock. Model the received
reference clock as an alternate parent of reference clock driver
clock. When received refclk is selected to output on cmn_refclk_p/m,
this is the internal reference clock driven on the pma_cmn_refclk_int.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210922123735.21927-5-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Model reference clock driver as a clock to enable derived refclk 2021-10-26T11:06:23+00:00 Swapnil Jakhade sjakhade@cadence.com 2021-09-22T12:37:34+00:00 235bde4f440a32a528bcedc48dbfa0ec4a039060 When reference clock driver is enabled, either derived or received refclk is output on cmn_refclk_p/m. Update the reference clock driver implementation by modelling reference clock driver as a "clock" with derived reference clock set as its default parent. The support for received reference clock will be added in a separate patch. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210922123735.21927-4-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
When reference clock driver is enabled, either derived or received refclk
is output on cmn_refclk_p/m. Update the reference clock driver
implementation by modelling reference clock driver as a "clock" with
derived reference clock set as its default parent. The support for
received reference clock will be added in a separate patch.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210922123735.21927-4-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Migrate to clk_hw based registration and OF APIs 2021-10-26T11:06:23+00:00 Swapnil Jakhade sjakhade@cadence.com 2021-09-22T12:37:32+00:00 aef096dbf514a9f70a1d81824d3b21d5266e0d6e Use clk_hw based provider APIs to register clks to remove the usage of deprecated APIs. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210922123735.21927-2-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Use clk_hw based provider APIs to register clks to remove the usage of
deprecated APIs.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210922123735.21927-2-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Check PIPE mode PHY status to be ready for operation 2021-08-17T10:12:44+00:00 Swapnil Jakhade sjakhade@cadence.com 2021-07-28T14:54:54+00:00 48ac6085bdfcf568e24c1efd45615ec3d5d3545b PIPE PHY status is used to communicate the completion of several PHY functions. Check if PHY is ready for operation while configured for PIPE mode during startup. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210728145454.15945-10-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
PIPE PHY status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-10-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add debug information for PHY configuration 2021-08-17T10:12:44+00:00 Swapnil Jakhade sjakhade@cadence.com 2021-07-28T14:54:53+00:00 84f55df836916be2b052a5000cca8d7d9fcf2520 Add debug information in probe regarding PHY configuration parameters like single link or multilink protocol along with number of lanes used for each protocol link. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210728145454.15945-9-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add debug information in probe regarding PHY configuration parameters
like single link or multilink protocol along with number of lanes
used for each protocol link.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-9-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add separate functions for reusable code 2021-08-17T10:12:44+00:00 Swapnil Jakhade sjakhade@cadence.com 2021-07-28T14:54:52+00:00 8f3ced2fd4906523e251f252dee03f6c22129e08 Torrent PHY driver currently supports single link DP configuration. Prepare driver to support multilink DP configurations by adding separate functions for common initialization sequence. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210728145454.15945-8-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Torrent PHY driver currently supports single link DP configuration.
Prepare driver to support multilink DP configurations by adding
separate functions for common initialization sequence.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210728145454.15945-8-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add PHY configuration for DP with 100MHz ref clock 2021-08-17T10:12:44+00:00 Swapnil Jakhade sjakhade@cadence.com 2021-07-28T14:54:51+00:00 1cc455150b7a67f3bbfe1dce03a97b4ae88778d5 Add PHY configuration registers for single link DP with 100MHz reference clock and NO_SSC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210728145454.15945-7-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add PHY configuration registers for single link DP with 100MHz reference
clock and NO_SSC.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-7-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add PHY registers for DP in array format 2021-08-17T10:12:44+00:00 Swapnil Jakhade sjakhade@cadence.com 2021-07-28T14:54:50+00:00 da055e5503893e27d6494f52bd6987f0da0c7658 Add PHY registers for single link DP in array format to simplify code and to improve readability. This supports already supported frequencies for DP of 19.2MHz and 25MHz. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210728145454.15945-6-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add PHY registers for single link DP in array format to simplify
code and to improve readability. This supports already supported
frequencies for DP of 19.2MHz and 25MHz.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-6-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Configure PHY registers as a function of input reference clock rate 2021-08-17T10:12:43+00:00 Swapnil Jakhade sjakhade@cadence.com 2021-07-28T14:54:49+00:00 6a2338a5bf7f9b4df5ed55d7b25ceb996ea09310 Torrent PHY supports multiple serdes standards with different input reference clock frequencies. PHY register values differ based on the reference clock rate. Add PHY input reference clock frequency as a new dimension to select proper register configuration. No functional change is intended. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210728145454.15945-5-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Torrent PHY supports multiple serdes standards with different input
reference clock frequencies. PHY register values differ based on the
reference clock rate. Add PHY input reference clock frequency as a
new dimension to select proper register configuration. No functional
change is intended.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-5-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add enum for supported input reference clock frequencies 2021-08-17T10:12:43+00:00 Swapnil Jakhade sjakhade@cadence.com 2021-07-28T14:54:48+00:00 3b40162516ca04209d750ddc174eea3e6deac148 Torrent PHY supports different input reference clock frequencies. Register configurations will be different based on reference clock value. Prepare driver to support such multiple reference clock frequencies. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210728145454.15945-4-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Torrent PHY supports different input reference clock frequencies.
Register configurations will be different based on reference clock value.
Prepare driver to support such multiple reference clock frequencies.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210728145454.15945-4-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>