linux-toradex.git/drivers/phy/microchip, branch v5.13-rc3 Linux kernel for Apalis and Colibri modules phy: fix resource_size.cocci warnings 2021-04-06T05:09:20+00:00 kernel test robot lkp@intel.com 2021-03-18T23:28:44+00:00 cbc336c09b6d6dfb24d20c955599123308fa2fe2 drivers/phy/microchip/sparx5_serdes.c:2440:54-57: ERROR: Missing resource_size with iores Use resource_size function on resource object instead of explicit computation. Generated by: scripts/coccinelle/api/resource_size.cocci Fixes: 2ff8a1eeb5aa ("phy: Add Sparx5 ethernet serdes PHY driver") CC: Steen Hegelund <steen.hegelund@microchip.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20210318232844.GA65886@63b0c5462fda Signed-off-by: Vinod Koul <vkoul@kernel.org> 
drivers/phy/microchip/sparx5_serdes.c:2440:54-57: ERROR: Missing resource_size with iores

 Use resource_size function on resource object
 instead of explicit computation.

Generated by: scripts/coccinelle/api/resource_size.cocci

Fixes: 2ff8a1eeb5aa ("phy: Add Sparx5 ethernet serdes PHY driver")
CC: Steen Hegelund <steen.hegelund@microchip.com>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20210318232844.GA65886@63b0c5462fda
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: Sparx5 Eth SerDes: Use direct register operations 2021-04-06T05:07:57+00:00 Steen Hegelund steen.hegelund@microchip.com 2021-03-29T14:13:09+00:00 8595ffb52fa3a1dd8620f0029a0e22ee37efd17f Use direct register operations instead of a table of register information to lower the stack usage. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20210329141309.612459-2-steen.hegelund@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Use direct register operations instead of a table of register
information to lower the stack usage.

Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20210329141309.612459-2-steen.hegelund@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: microchip: PHY_SPARX5_SERDES should depend on ARCH_SPARX5 2021-03-31T11:16:41+00:00 Geert Uytterhoeven geert+renesas@glider.be 2021-03-31T08:19:37+00:00 a113ef0a5e2eb3015da2e6dee0656d78e66fd691 The Microchip Sparx5 SerDes PHY is present only Microchip Sparx5 SoCs. Hence add a dependency on ARCH_SPARX5, to prevent asking the user about this driver when configuring a kernel without support for Sparx5 SoCs. Fixes: 2ff8a1eeb5aa8bb4 ("phy: Add Sparx5 ethernet serdes PHY driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210331081937.367408-1-geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org> 
The Microchip Sparx5 SerDes PHY is present only Microchip Sparx5 SoCs.
Hence add a dependency on ARCH_SPARX5, to prevent asking the user about
this driver when configuring a kernel without support for Sparx5 SoCs.

Fixes: 2ff8a1eeb5aa8bb4 ("phy: Add Sparx5 ethernet serdes PHY driver")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20210331081937.367408-1-geert+renesas@glider.be
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: Add Sparx5 ethernet serdes PHY driver 2021-03-17T06:43:19+00:00 Steen Hegelund steen.hegelund@microchip.com 2021-02-18T16:14:50+00:00 2ff8a1eeb5aa8bb471f3756a695b8b69841eb61f Add the Microchip Sparx5 ethernet serdes PHY driver for the 6G, 10G and 25G interfaces available in the Sparx5 SoC. Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20210218161451.3489955-4-steen.hegelund@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add the Microchip Sparx5 ethernet serdes PHY driver for the 6G, 10G and 25G
interfaces available in the Sparx5 SoC.

Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com>
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20210218161451.3489955-4-steen.hegelund@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>