linux-toradex.git/drivers/phy/xilinx, branch v6.10

phy: xilinx: Convert to platform remove callback returning void

2024-04-05T17:00:39+00:00

The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.

To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().

Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.

Signed-off-by: Uwe Kleine-König 
Acked-by: Michal Simek 
Link: https://lore.kernel.org/r/57a3338a1cec683ac84d48e00dbf197e15ee5481.1709886922.git.u.kleine-koenig@pengutronix.de
Signed-off-by: Vinod Koul

phy: constify of_phandle_args in xlate

2024-02-23T12:13:14+00:00

The xlate callbacks are supposed to translate of_phandle_args to proper
provider without modifying the of_phandle_args.  Make the argument
pointer to const for code safety and readability.

Signed-off-by: Krzysztof Kozlowski 
Acked-by: Thierry Reding 
Acked-by: Linus Walleij 
Acked-by: Florian Fainelli  #Broadcom
Link: https://lore.kernel.org/r/20240217093937.58234-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Vinod Koul

phy: zynqmp: Allow variation in refclk rate

2023-07-12T16:57:44+00:00

Due to limited available frequency ratios, the reference clock rate may
not be exactly the same as the required rate. Allow a small (100 ppm)
deviation.

Signed-off-by: Sean Anderson 
Link: https://lore.kernel.org/r/20230711194542.898230-1-sean.anderson@seco.com
Signed-off-by: Vinod Koul

phy: xilinx: phy-zynqmp: dynamic clock support for power-save

2023-07-12T16:57:42+00:00

Enabling clock for all the lanes consumes power even PHY is active or
inactive. To resolve this, enable/disable clocks in phy_init/phy_exit.

By default clock is disabled for all the lanes. Whenever phy_init called
from USB, SATA, or display driver, etc. It enabled the required clock
for requested lane. On phy_exit cycle, it disabled clock for the active
PHYs.

During the suspend/resume cycle, each USB/ SATA/ display driver called
phy_exit/phy_init individually. It disabled clock on exit, and enabled
on initialization for the active PHYs.

Signed-off-by: Piyush Mehta 
Link: https://lore.kernel.org/r/20230613140250.3018947-3-piyush.mehta@amd.com
Signed-off-by: Vinod Koul

phy: xilinx: add runtime PM support

2023-07-12T16:57:42+00:00

Added Runtime power management support to the xilinx phy driver and using
DEFINE_RUNTIME_DEV_PM_OPS new macros allows the compiler to remove the
unused dev_pm_ops structure and related functions if !CONFIG_PM without
the need to mark the functions __maybe_unused.

Signed-off-by: Piyush Mehta 
Link: https://lore.kernel.org/r/20230613140250.3018947-2-piyush.mehta@amd.com
Signed-off-by: Vinod Koul

phy: xilinx: phy-zynqmp: mention SGMII as supported protocol

2023-03-31T13:38:48+00:00

SGMII is validated on kria KR260 robotics starter kit. So modify the
comment description to include it in supported controllers list.

Signed-off-by: Radhey Shyam Pandey 
Reviewed-by: Laurent Pinchart 
Link: https://lore.kernel.org/r/1679940407-13131-1-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Vinod Koul

phy: xilinx: zynqmp: Fix bus width setting for SGMII

2022-01-27T05:25:26+00:00

TX_PROT_BUS_WIDTH and RX_PROT_BUS_WIDTH are single registers with
separate bit fields for each lane. The code in xpsgtr_phy_init_sgmii was
not preserving the existing register value for other lanes, so enabling
the PHY in SGMII mode on one lane zeroed out the settings for all other
lanes, causing other PS-GTR peripherals such as USB3 to malfunction.

Use xpsgtr_clr_set to only manipulate the desired bits in the register.

Fixes: 4a33bea00314 ("phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver")
Signed-off-by: Robert Hancock 
Acked-by: Michal Simek 
Reviewed-by: Laurent Pinchart 
Link: https://lore.kernel.org/r/20220126001600.1592218-1-robert.hancock@calian.com
Signed-off-by: Vinod Koul

phy: xilinx: zynqmp: skip PHY initialization and PLL lock for USB

2021-08-18T10:14:14+00:00

PHY initialization for USB is required on linux boot or when
gt lane is changed from the current one and it is applicable
on PLL lock too.

Signed-off-by: Piyush Mehta 
Link: https://lore.kernel.org/r/20210818084311.2643986-1-piyush.mehta@xilinx.com
Signed-off-by: Vinod Koul

phy: zynqmp: Handle the clock enable/disable properly

2021-03-31T12:55:54+00:00

The current driver is not handling the clock enable/disable operations
properly. The clocks need to be handled correctly by enabling or
disabling at appropriate places. This patch adds code to handle the
same.

Signed-off-by: Manish Narani 
Reviewed-by: Laurent Pinchart 
Acked-by: Michal Simek 
Link: https://lore.kernel.org/r/1616588325-95602-1-git-send-email-manish.narani@xilinx.com
Signed-off-by: Vinod Koul

phy: zynqmp: Simplify code by using dev_err_probe()

2021-02-06T09:58:15+00:00

Use already prepared dev_err_probe() introduced by commit a787e5400a1c
("driver core: add device probe log helper").
It simplifies EPROBE_DEFER handling.

Signed-off-by: Michal Simek 
Link: https://lore.kernel.org/r/0df30548f721b10475a6cc5659beda102fec3c87.1612444300.git.michal.simek@xilinx.com
Signed-off-by: Vinod Koul