linux-toradex.git/drivers/pinctrl/intel, branch v4.13-rc5

pinctrl: intel: merrifield: Correct UART pin lists

2017-08-07T13:23:11+00:00

UART pin lists consist GPIO numbers which is simply wrong.
Replace it by pin numbers.

Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Signed-off-by: Andy Shevchenko 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij

pinctrl: cherryview: Add Setzer models to the Chromebook DMI quirk

2017-08-03T08:18:34+00:00

Add one more model to the Chromebook DMI quirk to make it working again.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=194945
Fixes: 2a8209fa6823 ("pinctrl: cherryview: Extend the Chromebook DMI quirk to Intel_Strago systems")
Reported-by: mail@abhishek.geek.nz
Signed-off-by: Andy Shevchenko 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij

Merge tag 'v4.12-rc7' into devel

2017-06-29T12:27:39+00:00

Linux 4.12-rc7

pinctrl: intel: Add Intel Cannon Lake PCH pin controller support

2017-06-09T11:03:47+00:00

This adds pinctrl/GPIO support for Intel Cannon Lake PCH. The Cannon
Lake PCH GPIO is based on newer version of the Intel GPIO hardware.

Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Linus Walleij

pinctrl: intel: Make it possible to specify mode per pin in a group

2017-06-09T11:02:50+00:00

On some SoCs not all pins in a group use the same mode when a certain
function is muxed out of them. This makes it possible to specify mode per
pin as an array instead in addition to single integer.

Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Linus Walleij

pinctrl: intel: Add support for variable size pad groups

2017-06-09T11:01:35+00:00

The Intel GPIO hardware has a concept of pad groups, which means 1 to 32
pads occupying their own GPI_IS, GPI_IE, PAD_OWN and so on registers. The
existing hardware has the same amount of pads in each pad group (except the
last one) so it is possible to use community->gpp_size to calculate start
offset of each register.

With the next generation SoCs the pad group size is not always the same
anymore which means we cannot use community->gpp_size for register offset
calculations directly.

To support variable size pad groups we introduce struct intel_padgroup that
can be filled in by the client drivers according the hardware pad group
layout. The core driver will always use these when it performs calculations
for pad register offsets. The core driver will automatically populate pad
groups based on community->gpp_size if the driver does not provide any.
This makes sure the existing drivers still work as expected.

Signed-off-by: Mika Westerberg 
Signed-off-by: Chuah, Kim Tatt 
Signed-off-by: Tan Jui Nee 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Linus Walleij

pinctrl: cherryview: Extend the Chromebook DMI quirk to Intel_Strago systems

2017-05-23T08:08:40+00:00

It turns out there are quite many Chromebooks out there that have the
same keyboard issue than Acer Chromebook. All of them are based on
Intel_Strago reference and report their DMI_PRODUCT_FAMILY as
"Intel_Strago" (Samsung Chromebook 3 and Cyan Chromebooks are exceptions
for which we add separate entries).

Instead of adding each machine to the quirk table, we use
DMI_PRODUCT_FAMILY of "Intel_Strago" that hopefully covers most of the
machines out there currently.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=194945
Suggested: Dmitry Torokhov 
Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Linus Walleij

pinctrl: cherryview: Add terminate entry for dmi_system_id tables

2017-05-22T08:39:10+00:00

Make sure dmi_system_id tables are NULL terminated.

Fixes: 703650278372 ("pinctrl: cherryview: Add a quirk to make Acer
Chromebook keyboard work again")
Signed-off-by: Wei Yongjun 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2017-05-03T00:59:33+00:00

Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.12 cycle.

The extra week before the merge window actually resulted in some of
the type of fixes that usually arrive after the merge window already
starting to trickle in from eager developers using -next, I'm
impressed.

I have recruited a Samsung subsubsystem maintainer (Krzysztof) to deal
with the onset of Samsung patches. It works great.

Apart from that it is a boring round, just incremental updates and
fixes all over the place, no serious core changes or anything exciting
like that. The most pleasing to see is Julia Cartwrights work to audit
the irqchip-providing drivers for realtime locking compliance. It's
one of those "I should really get around to looking into that" things
that have been on my TODO list since forever.

Summary:

Core changes:

- add bi-directional and output-enable pin configurations to the
generic bindings and generic pin controlling core.

New drivers or subdrivers:

- Armada 37xx SoC pin controller and GPIO support.

- Axis ARTPEC-6 SoC pin controller support.

- AllWinner A64 R_PIO controller support, and opening up the
AllWinner sunxi driver for ARM64 use.

- Rockchip RK3328 support.

- Renesas R-Car H3 ES2.0 support.

- STM32F469 support in the STM32 driver.

- Aspeed G4 and G5 pin controller support.

Improvements:

- a whole slew of realtime improvements to drivers implementing
irqchips: BCM, AMD, SiRF, sunxi, rockchip.

- switch meson driver to get the GPIO ranges from the device tree.

- input schmitt trigger support on the Rockchip driver.

- enable the sunxi (AllWinner) driver to also be used on ARM64
silicon.

- name the Qualcomm QDF2xxx GPIO lines.

- support GMMR GPIO regions on the Intel Cherryview. This fixes a
serialization problem on these platforms.

- pad retention support for the Samsung Exynos 5433.

- handle suspend-to-ram in the AT91-pio4 driver.

- pin configuration support in the Aspeed driver.

Cleanups:

- the final name of Rockchip RK1108 was RV1108 so rename the driver
and variables to stay consistent"

* tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
pinctrl: mediatek: Add missing pinctrl bindings for mt7623
pinctrl: artpec6: Fix return value check in artpec6_pmx_probe()
pinctrl: artpec6: Remove .owner field for driver
pinctrl: tegra: xusb: Silence sparse warnings
ARM: at91/at91-pinctrl documentation: fix spelling mistake: "contoller" -> "controller"
pinctrl: make artpec6 explicitly non-modular
pinctrl: aspeed: g5: Add pinconf support
pinctrl: aspeed: g4: Add pinconf support
pinctrl: aspeed: Add core pinconf support
pinctrl: aspeed: Document pinconf in devicetree bindings
pinctrl: Add st,stm32f469-pinctrl compatible to stm32-pinctrl
pinctrl: stm32: Add STM32F469 MCU support
Documentation: dt: Remove ngpios from stm32-pinctrl binding
pinctrl: stm32: replace device_initcall() with arch_initcall()
pinctrl: stm32: add possibility to use gpio-ranges to declare bank range
pinctrl: armada-37xx: Add gpio support
pinctrl: armada-37xx: Add pin controller support for Armada 37xx
pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
pinctrl: core: Make pinctrl_init_controller() static
pinctrl: generic: Add bi-directional and output-enable
...

pinctrl: cherryview: Add a quirk to make Acer Chromebook keyboard work again

2017-04-11T08:09:39+00:00

After commit 47c950d10202 ("pinctrl: cherryview: Do not add all
southwest and north GPIOs to IRQ domain") the driver does not add all
GPIOs to the irqdomain. The reason for that is that those GPIOs cannot
generate IRQs at all, only GPEs (General Purpose Events). This causes
Linux virtual IRQ numbering to change.

However, it seems some CYAN Chromebooks, including Acer Chromebook
hardcodes these Linux IRQ numbers in the ACPI tables of the machine.
Since the numbering is different now, the IRQ meant for keyboard does
not match the Linux virtual IRQ number anymore making the keyboard
non-functional.

Work this around by adding special quirk just for these machines where
we add back all GPIOs to the irqdomain. Rest of the Cherryview/Braswell
based machines will not be affected by the change.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=194945
Fixes: 47c950d10202 ("pinctrl: cherryview: Do not add all southwest and north GPIOs to IRQ domain")
Reported-by: Adam S Levy 
Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij