linux-toradex.git/drivers/pinctrl/intel, branch v4.4.73

pinctrl: cherryview: Do not mask all interrupts in probe

2017-03-26T10:13:17+00:00

commit bcb48cca23ec9852739e4a464307fa29515bbe48 upstream.

The Cherryview GPIO controller has 8 or 16 wires connected to the I/O-APIC
which can be used directly by the platform/BIOS or drivers. One such wire
is used as SCI (System Control Interrupt) which ACPI depends on to be able
to trigger GPEs (General Purpose Events).

The pinctrl driver itself uses another IRQ resource which is wire OR of all
the 8 (or 16) wires and follows what BIOS has programmed to the IntSel
register of each pin.

Currently the driver masks all interrupts at probe time and this prevents
these direct interrupts from working as expected. The reason for this is
that some early stage prototypes had some pins misconfigured causing lots
of spurious interrupts.

We fix this by leaving the interrupt mask untouched. This allows SCI and
other direct interrupts work properly. What comes to the possible spurious
interrupts we switch the default handler to be handle_bad_irq() instead of
handle_simple_irq() (which was not correct anyway).

Reported-by: Yu C Chen 
Reported-by: Anisse Astier 
Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij 
Cc: Sumit Semwal 
Signed-off-by: Greg Kroah-Hartman

pinctrl: broxton: Use correct PADCFGLOCK offset

2017-02-01T07:30:54+00:00

commit ecc8995363ee6231b32dad61c955b371b79cc4cf upstream.

PADCFGLOCK (and PADCFGLOCK_TX) offset in Broxton actually starts at 0x060
and not 0x090 as used in the driver. Fix it to use the correct offset.

Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Linus Walleij 
Signed-off-by: Greg Kroah-Hartman

pinctrl: cherryview: Prevent possible interrupt storm on resume

2016-11-18T09:48:34+00:00

commit d2cdf5dc58f6970e9d9d26e47974c21fe87983f3 upstream.

When the system is suspended to S3 the BIOS might re-initialize certain
GPIO pins back to their original state or it may re-program interrupt mask
of others. For example Acer TravelMate B116-M had BIOS bug where certain
GPIO pin (MF_ISH_GPIO_5) was programmed to trigger on high level, and the
pin state was high once the BIOS gave control to the OS on resume.

This triggers lots of messages like:

 irq 117, desc: ffff88017a61e600, depth: 1, count: 0, unhandled: 0
 ->handle_irq():  ffffffff8109b613, handle_bad_irq+0x0/0x1e0
 ->irq_data.chip(): ffffffffa0020180, chv_pinctrl_exit+0x2d84/0x12 [pinctrl_cherryview]
 ->action():           (null)
    IRQ_NOPROBE set

We reset the mask back to known state in chv_pinctrl_resume() but that is
called only after device interrupts have already been enabled.

Now, this particular issue was fixed by upgrading the BIOS to the latest
(v1.23) but not everybody upgrades their BIOSes so we fix it up in the
driver as well.

Prevent the possible interrupt storm by moving suspend and resume hooks to
be called at _noirq time instead. Since device interrupts are still
disabled we can restore the mask back to known state before interrupt storm
happens.

Reported-by: Christian Steiner 
Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij 
Signed-off-by: Greg Kroah-Hartman

pinctrl: cherryview: Serialize register access in suspend/resume

2016-11-18T09:48:34+00:00

commit 56211121c0825cd188caad05574fdc518d5cac6f upstream.

If async suspend is enabled, the driver may access registers concurrently
with another instance which may fail because of the bug in Cherryview GPIO
hardware. Prevent this by taking the shared lock while accessing the
hardware in suspend and resume hooks.

Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij 
Signed-off-by: Greg Kroah-Hartman

pinctrl: cherryview: prevent concurrent access to GPIO controllers

2016-08-20T16:09:17+00:00

commit 0bd50d719b004110e791800450ad204399100a86 upstream.

Due to a silicon issue on the Atom X5-Z8000 "Cherry Trail" processor
series, a common lock must be used to prevent concurrent accesses
across the 4 GPIO controllers managed by this driver.

See Intel Atom Z8000 Processor Series Specification Update
(Rev. 005), errata #CHT34, for further information.

Signed-off-by: Dan O'Donovan 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij 
Signed-off-by: Greg Kroah-Hartman

pinctrl: intel: fix offset calculation issue of register PAD_OWN

2015-12-10T22:01:42+00:00

The calculation equation of PAD_OWN register offset is not
correct for Broxton, verified this fix will get right
offset for Broxton.

Signed-off-by: Qi Zheng 
Signed-off-by: Qipeng Zha 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij

pinctrl: intel: fix bug of register offset calculation

2015-12-10T22:01:41+00:00

The group size for registers PADCFGLOCK, HOSTSW_OWN, GPI_IS,
GPI_IE, are not 24 for Broxton, Add a parameter to allow
different platform to set correct value.

Signed-off-by: Qi Zheng 
Signed-off-by: Qipeng Zha 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij

Merge tag 'gpio-v4.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

2015-11-02T20:59:12+00:00

Pull GPIO updates from Linus Walleij:
"Here is the bulk of GPIO changes for the v4.4 development cycle.

The only changes hitting outside drivers/gpio are in the pin control
subsystem and these seem to have settled nicely in linux-next.

Development mistakes and catfights are nicely documented in the
reverts as you can see. The outcome of the ABI fight is that we're
working on a chardev ABI for GPIO now, where hope to show results for
the v4.5 kernel.

Summary of changes:

GPIO core:
- Define and handle flags for open drain/open collector and open
source/open emitter, also know as "single-ended" configurations.
- Generic request/free operations that handle calling out to the
(optional) pin control backend.
- Some refactoring related to an ABI change that did not happen, yet
provide useful.
- Added a real-time compliance checklist. Many GPIO chips have
irqchips, and need to think this over with the RT patches going
upstream.
- Restructure, fix and clean up Kconfig menus a bit.

New drivers:
- New driver for AMD Promony.
- New driver for ACCES 104-IDIO-16, a port-mapped I/O card,
ISA-style. Very retro.

Subdriver changes:
- OMAP changes to handle real time requirements.
- Handle trigger types for edge and level IRQs on PL061 properly. As
this hardware is very common it needs to set a proper example for
others to follow.
- Some container_of() cleanups.
- Delete the unused MSM driver in favor of the driver that is
embedded inside the pin control driver.
- Cleanup of the ath79 GPIO driver used by many, many OpenWRT router
targets.
- A consolidated IT87xx driver replacing the earlier very specific
IT8761e driver.
- Handle the TI TCA9539 in the PCA953x driver. Also handle ACPI
devices in this subdriver.
- Drop xilinx arch dependencies as these FPGAs seem to profilate over
a few different architectures. MIPS and ARM come to mind"

* tag 'gpio-v4.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (57 commits)
gpio: fix up SPI submenu
gpio: drop surplus I2C dependencies
gpio: drop surplus X86 dependencies
gpio: dt-bindings: document the official use of "ngpios"
gpio: MAINTAINERS: Add an entry for the ATH79 GPIO driver
gpio / ACPI: Allow shared GPIO event to be read via operation region
gpio: group port-mapped I/O drivers in a menu
gpio: Add ACCES 104-IDIO-16 driver maintainer entry
gpio: zynq: Document interrupt-controller DT binding
gpio: xilinx: Drop architecture dependencies
gpio: generic: Revert to old error handling in bgpio_map
gpio: add a real time compliance notes
Revert "gpio: add a real time compliance checklist"
gpio: Add GPIO support for the ACCES 104-IDIO-16
gpio: driver for AMD Promontory
gpio: xlp: Convert to use gpiolib irqchip helpers
gpio: add a real time compliance checklist
gpio/xilinx: enable for MIPS
gpiolib: Add and use OF_GPIO_SINGLE_ENDED flag
gpiolib: Split GPIO flags parsing and GPIO configuration
...

pinctrl: intel: Add Intel Broxton pin controller support

2015-10-27T12:32:13+00:00

This driver adds pinctrl/GPIO support for Intel Broxton. The GPIO
controller is based on the same hardware design that is already used in
Intel Sunrisepoint so we leverage the core driver here.

Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij

pinctrl: intel: Allow requesting pins which are in ACPI mode as GPIOs

2015-10-27T12:30:56+00:00

Reserved for ACPI actually means that in such case the GPIO hardware will
not update the interrupt status register (GPI_IS) even if the pin is
configured to trigger an interrupt. It will update GPI_GPE_STS instead and
does not trigger an interrupt.

Allow using such pins as GPIOs, only prevent their usage as interrupts.

We also rename function intel_pad_reserved_for_acpi() to be
intel_pad_acpi_mode() which reflects the actual meaning better.

Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij