linux-toradex.git/drivers/pinctrl/intel, branch v4.8-rc1 Linux kernel for Apalis and Colibri modules Merge tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 2016-07-29T00:06:51+00:00 Linus Torvalds torvalds@linux-foundation.org 2016-07-29T00:06:51+00:00 d94ba9e7d8d5c821d0442f13b30b0140c1109c38 Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.8 kernel cycle. Nothing stands out as especially exiting: new drivers, new subdrivers, lots of cleanups and incremental features. Business as usual. New drivers: - New driver for Oxnas pin control and GPIO. This ARM-based chipset is used in a few storage (NAS) type devices. - New driver for the MAX77620/MAX20024 pin controller portions. - New driver for the Intel Merrifield pin controller. New subdrivers: - New subdriver for the Qualcomm MDM9615 - New subdriver for the STM32F746 MCU - New subdriver for the Broadcom NSP SoC. Cleanups: - Demodularization of bool compiled-in drivers. Apart from this there is just regular incremental improvements to a lot of drivers, especially Uniphier and PFC" * tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (131 commits) pinctrl: fix pincontrol definition for marvell pinctrl: xway: fix typo Revert "pinctrl: amd: make it explicitly non-modular" pinctrl: iproc: Add NSP and Stingray GPIO support pinctrl: Update iProc GPIO DT bindings pinctrl: bcm: add OF dependencies pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe() pinctrl: Add STM32F746 MCU support pinctrl: intel: Protect set wake flow by spin lock pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe() pinctrl: uniphier: add Ethernet pin-mux settings sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the code pinctrl: ns2: fix return value check in ns2_pinmux_probe() pinctrl: qcom: update DT bindings with ebi2 groups pinctrl: qcom: establish proper EBI2 pin groups pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macro Documentation: dt: Add new compatible to STM32 pinctrl driver bindings includes: dt-bindings: Add STM32F746 pinctrl DT bindings pinctrl: sunxi: fix nand0 function name for sun8i pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11 ... 
Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.8 kernel cycle.

  Nothing stands out as especially exiting: new drivers, new subdrivers,
  lots of cleanups and incremental features.

  Business as usual.

  New drivers:

   - New driver for Oxnas pin control and GPIO.  This ARM-based chipset
     is used in a few storage (NAS) type devices.

   - New driver for the MAX77620/MAX20024 pin controller portions.

   - New driver for the Intel Merrifield pin controller.

  New subdrivers:

   - New subdriver for the Qualcomm MDM9615

   - New subdriver for the STM32F746 MCU

   - New subdriver for the Broadcom NSP SoC.

  Cleanups:

   - Demodularization of bool compiled-in drivers.

  Apart from this there is just regular incremental improvements to a
  lot of drivers, especially Uniphier and PFC"

* tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (131 commits)
  pinctrl: fix pincontrol definition for marvell
  pinctrl: xway: fix typo
  Revert "pinctrl: amd: make it explicitly non-modular"
  pinctrl: iproc: Add NSP and Stingray GPIO support
  pinctrl: Update iProc GPIO DT bindings
  pinctrl: bcm: add OF dependencies
  pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe()
  pinctrl: Add STM32F746 MCU support
  pinctrl: intel: Protect set wake flow by spin lock
  pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe()
  pinctrl: uniphier: add Ethernet pin-mux settings
  sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the code
  pinctrl: ns2: fix return value check in ns2_pinmux_probe()
  pinctrl: qcom: update DT bindings with ebi2 groups
  pinctrl: qcom: establish proper EBI2 pin groups
  pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macro
  Documentation: dt: Add new compatible to STM32 pinctrl driver bindings
  includes: dt-bindings: Add STM32F746 pinctrl DT bindings
  pinctrl: sunxi: fix nand0 function name for sun8i
  pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11
  ...
pinctrl: intel: Protect set wake flow by spin lock 2016-07-11T09:15:33+00:00 Andy Shevchenko andriy.shevchenko@linux.intel.com 2016-07-08T11:30:46+00:00 9a520fd99f2c3feb178d6d05e347beb9017dc07b It seems intel_gpio_irq_wake() misses lock protection against I/O flow. Use spin lock here as well. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
It seems intel_gpio_irq_wake() misses lock protection against I/O flow.
Use spin lock here as well.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: intel: Add Intel Merrifield pin controller support 2016-06-29T07:59:35+00:00 Andy Shevchenko andriy.shevchenko@linux.intel.com 2016-06-23T10:49:36+00:00 4e80c8f505741cbdef3e10862ea36057e8d85e7c This driver adds pinctrl support for Intel Merrifield. The IP block which is called Family-Level Interface Shim is a separate entity in SoC. The GPIO driver (gpio-intel-mid.c) will be updated accordingly to support pinctrl interface. Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
This driver adds pinctrl support for Intel Merrifield. The IP block which is
called Family-Level Interface Shim is a separate entity in SoC. The GPIO driver
(gpio-intel-mid.c) will be updated accordingly to support pinctrl interface.

Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: baytrail: Fix mingled clock pins 2016-06-23T09:05:04+00:00 Cristina Ciocan cristina.ciocan@intel.com 2016-06-22T11:17:19+00:00 b41aa4f8476545e2b663b1549759a8c3a66f47b0 Fix plt clock 3, 4 and 5 pins, which were not in the proper order. Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Fix plt clock 3, 4 and 5 pins, which were not in the proper order.

Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: intel: Prevent force threading of the interrupt handler 2016-06-18T08:35:47+00:00 Mika Westerberg mika.westerberg@linux.intel.com 2016-06-16T08:25:37+00:00 1a7d1cb81eb2519de1359d35cbcade4da41b638d The pinctrl-intel needs to use request_irq() instead of chained interrupt handling because it shares the interrupt with multiple GPIO host controllers found on Intel CPUs. In -rt all such interrupts are forced to run in thread context which triggers following warning: WARNING: CPU: 0 PID: 530 at kernel/irq/handle.c:151 handle_irq_event_percpu+0x23d/0x240 irq 348 handler irq_default_primary_handler+0x0/0x10 enabled interrupts Modules linked in: CPU: 0 PID: 530 Comm: irq/14-INT3452: Not tainted 4.6.2-rt5 #1060 0000000000000000 ffff88007a257c98 ffffffff812d8494 ffff88007a257ce8 0000000000000000 ffff88007a257cd8 ffffffff8105e554 000000977a257d90 ffff88007a37a380 000000000000015c 0000000000000002 0000000000000000 Call Trace: [<ffffffff812d8494>] dump_stack+0x4f/0x6b [<ffffffff8105e554>] __warn+0xe4/0x100 [<ffffffff8105e5bf>] warn_slowpath_fmt+0x4f/0x60 [<ffffffff810b18f0>] ? __synchronize_hardirq+0x60/0x60 [<ffffffff810b17fd>] handle_irq_event_percpu+0x23d/0x240 [<ffffffff810b1862>] handle_irq_event+0x62/0x90 [<ffffffff810b4e1f>] handle_edge_irq+0x8f/0x190 [<ffffffff810b0d82>] generic_handle_irq+0x22/0x30 [<ffffffff81307abc>] intel_gpio_irq+0xdc/0x150 [<ffffffff810b2293>] irq_forced_thread_fn+0x23/0x70 [<ffffffff810b250b>] irq_thread+0x13b/0x1d0 [<ffffffff8167b844>] ? __schedule+0x2e4/0x5a0 [<ffffffff810b2270>] ? irq_finalize_oneshot.part.37+0xd0/0xd0 [<ffffffff810b25a0>] ? irq_thread+0x1d0/0x1d0 [<ffffffff810b23d0>] ? wake_threads_waitq+0x30/0x30 [<ffffffff8107e624>] kthread+0xd4/0xf0 [<ffffffff8167ec27>] ? _raw_spin_unlock_irq+0x17/0x40 [<ffffffff8167f592>] ret_from_fork+0x22/0x40 [<ffffffff8107e550>] ? kthread_worker_fn+0x190/0x190 The handle_irq_event_* functions (and I suppose generic_handle_irq()) is expected to be called with interrupts disabled and they rightfully complain here because we run in thread context with interrupts enabled. Fix this by adding IRQF_NO_THREAD flag when the master interrupt is requested. This prevents forced threading of the interrupt used by the GPIO host controllers. Reported-by: Kim Tatt Chuah <kim.tatt.chuah@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
The pinctrl-intel needs to use request_irq() instead of chained interrupt
handling because it shares the interrupt with multiple GPIO host
controllers found on Intel CPUs. In -rt all such interrupts are forced to
run in thread context which triggers following warning:

 WARNING: CPU: 0 PID: 530 at kernel/irq/handle.c:151 handle_irq_event_percpu+0x23d/0x240
 irq 348 handler irq_default_primary_handler+0x0/0x10 enabled interrupts
 Modules linked in:
 CPU: 0 PID: 530 Comm: irq/14-INT3452: Not tainted 4.6.2-rt5 #1060
  0000000000000000 ffff88007a257c98 ffffffff812d8494 ffff88007a257ce8
  0000000000000000 ffff88007a257cd8 ffffffff8105e554 000000977a257d90
  ffff88007a37a380 000000000000015c 0000000000000002 0000000000000000
 Call Trace:
  [<ffffffff812d8494>] dump_stack+0x4f/0x6b
  [<ffffffff8105e554>] __warn+0xe4/0x100
  [<ffffffff8105e5bf>] warn_slowpath_fmt+0x4f/0x60
  [<ffffffff810b18f0>] ? __synchronize_hardirq+0x60/0x60
  [<ffffffff810b17fd>] handle_irq_event_percpu+0x23d/0x240
  [<ffffffff810b1862>] handle_irq_event+0x62/0x90
  [<ffffffff810b4e1f>] handle_edge_irq+0x8f/0x190
  [<ffffffff810b0d82>] generic_handle_irq+0x22/0x30
  [<ffffffff81307abc>] intel_gpio_irq+0xdc/0x150
  [<ffffffff810b2293>] irq_forced_thread_fn+0x23/0x70
  [<ffffffff810b250b>] irq_thread+0x13b/0x1d0
  [<ffffffff8167b844>] ? __schedule+0x2e4/0x5a0
  [<ffffffff810b2270>] ? irq_finalize_oneshot.part.37+0xd0/0xd0
  [<ffffffff810b25a0>] ? irq_thread+0x1d0/0x1d0
  [<ffffffff810b23d0>] ? wake_threads_waitq+0x30/0x30
  [<ffffffff8107e624>] kthread+0xd4/0xf0
  [<ffffffff8167ec27>] ? _raw_spin_unlock_irq+0x17/0x40
  [<ffffffff8167f592>] ret_from_fork+0x22/0x40
  [<ffffffff8107e550>] ? kthread_worker_fn+0x190/0x190

The handle_irq_event_* functions (and I suppose generic_handle_irq()) is
expected to be called with interrupts disabled and they rightfully complain
here because we run in thread context with interrupts enabled.

Fix this by adding IRQF_NO_THREAD flag when the master interrupt is
requested. This prevents forced threading of the interrupt used by the GPIO
host controllers.

Reported-by: Kim Tatt Chuah <kim.tatt.chuah@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: intel: Use raw_spinlock for locking 2016-06-18T08:35:44+00:00 Mika Westerberg mika.westerberg@linux.intel.com 2016-06-16T08:25:36+00:00 27d9098cff6e7491617890d0e93632181a532ff3 When running -rt kernel and GPIO interrupt happens we get following BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:931 in_atomic(): 1, irqs_disabled(): 0, pid: 530, name: irq/14-INT3452: Preemption disabled at:[<ffffffff810b4dab>] handle_edge_irq+0x1b/0x190 CPU: 0 PID: 530 Comm: irq/14-INT3452: Not tainted 4.6.2-rt5 #1060 0000000000000000 ffff88007a257d58 ffffffff812d8494 0000000000000000 ffff88017a330000 ffff88007a257d78 ffffffff81083a11 ffff88007a252430 ffff88007a252430 ffff88007a257d90 ffffffff8167ef20 000000000000001a Call Trace: [<ffffffff812d8494>] dump_stack+0x4f/0x6b [<ffffffff81083a11>] ___might_sleep+0xe1/0x160 [<ffffffff8167ef20>] rt_spin_lock+0x20/0x50 [<ffffffff81308c6d>] intel_gpio_irq_ack+0x2d/0x80 [<ffffffff810b4e0b>] handle_edge_irq+0x7b/0x190 [<ffffffff810b0d82>] generic_handle_irq+0x22/0x30 [<ffffffff81307abc>] intel_gpio_irq+0xdc/0x150 [<ffffffff810b2293>] irq_forced_thread_fn+0x23/0x70 [<ffffffff810b250b>] irq_thread+0x13b/0x1d0 [<ffffffff8167b844>] ? __schedule+0x2e4/0x5a0 [<ffffffff810b2270>] ? irq_finalize_oneshot.part.37+0xd0/0xd0 [<ffffffff810b25a0>] ? irq_thread+0x1d0/0x1d0 [<ffffffff810b23d0>] ? wake_threads_waitq+0x30/0x30 [<ffffffff8107e624>] kthread+0xd4/0xf0 [<ffffffff8167ec27>] ? _raw_spin_unlock_irq+0x17/0x40 [<ffffffff8167f592>] ret_from_fork+0x22/0x40 [<ffffffff8107e550>] ? kthread_worker_fn+0x190/0x190 The reason why this happens is because intel_gpio_irq_ack() is called with desc->lock raw_spinlock locked which cannot sleep but our normal spinlock (which is converted to rtmutex in -rt) is allowed to sleep. This causes might_sleep() to trigger. Fix this by converting the normal spinlock to a raw_spinlock. Reported-by: Kim Tatt Chuah <kim.tatt.chuah@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
When running -rt kernel and GPIO interrupt happens we get following

 BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:931
 in_atomic(): 1, irqs_disabled(): 0, pid: 530, name: irq/14-INT3452:
 Preemption disabled at:[<ffffffff810b4dab>] handle_edge_irq+0x1b/0x190

 CPU: 0 PID: 530 Comm: irq/14-INT3452: Not tainted 4.6.2-rt5 #1060
  0000000000000000 ffff88007a257d58 ffffffff812d8494 0000000000000000
  ffff88017a330000 ffff88007a257d78 ffffffff81083a11 ffff88007a252430
  ffff88007a252430 ffff88007a257d90 ffffffff8167ef20 000000000000001a
 Call Trace:
  [<ffffffff812d8494>] dump_stack+0x4f/0x6b
  [<ffffffff81083a11>] ___might_sleep+0xe1/0x160
  [<ffffffff8167ef20>] rt_spin_lock+0x20/0x50
  [<ffffffff81308c6d>] intel_gpio_irq_ack+0x2d/0x80
  [<ffffffff810b4e0b>] handle_edge_irq+0x7b/0x190
  [<ffffffff810b0d82>] generic_handle_irq+0x22/0x30
  [<ffffffff81307abc>] intel_gpio_irq+0xdc/0x150
  [<ffffffff810b2293>] irq_forced_thread_fn+0x23/0x70
  [<ffffffff810b250b>] irq_thread+0x13b/0x1d0
  [<ffffffff8167b844>] ? __schedule+0x2e4/0x5a0
  [<ffffffff810b2270>] ? irq_finalize_oneshot.part.37+0xd0/0xd0
  [<ffffffff810b25a0>] ? irq_thread+0x1d0/0x1d0
  [<ffffffff810b23d0>] ? wake_threads_waitq+0x30/0x30
  [<ffffffff8107e624>] kthread+0xd4/0xf0
  [<ffffffff8167ec27>] ? _raw_spin_unlock_irq+0x17/0x40
  [<ffffffff8167f592>] ret_from_fork+0x22/0x40
  [<ffffffff8107e550>] ? kthread_worker_fn+0x190/0x190

The reason why this happens is because intel_gpio_irq_ack() is called with
desc->lock raw_spinlock locked which cannot sleep but our normal spinlock
(which is converted to rtmutex in -rt) is allowed to sleep. This causes
might_sleep() to trigger.

Fix this by converting the normal spinlock to a raw_spinlock.

Reported-by: Kim Tatt Chuah <kim.tatt.chuah@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl/broxton: enable platform device in the absence of ACPI enumeration 2016-06-15T06:37:42+00:00 Tan Jui Nee jui.nee.tan@intel.com 2016-06-07T06:55:51+00:00 0c3013bbe1d80035dc58336c4c7fdb18a32931df This is to cater the need for non-ACPI system whereby a platform device has to be created in order to bind with the Apollo Lake Pinctrl GPIO platform driver. Signed-off-by: Tan Jui Nee <jui.nee.tan@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
This is to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind
with the Apollo Lake Pinctrl GPIO platform driver.

Signed-off-by: Tan Jui Nee <jui.nee.tan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: cherryview: add handlers for pin_config_group_get/set 2016-06-15T06:37:40+00:00 Dan O'Donovan dan@emutex.com 2016-06-10T12:23:36+00:00 77401d7fdfcdcb233864f7a6edc1e15b4f5d56d9 Pin config get/set handlers for pin groups were previously not implemented by this driver. The pin_config_group_set is particularly useful for applying a common config setting to all pins in a specified group with a single call, without the caller needing to reference each individual pin by name. Signed-off-by: Dan O'Donovan <dan@emutex.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Pin config get/set handlers for pin groups were previously not
implemented by this driver.  The pin_config_group_set is
particularly useful for applying a common config setting to all
pins in a specified group with a single call, without the caller
needing to reference each individual pin by name.

Signed-off-by: Dan O'Donovan <dan@emutex.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: cherryview: add option to set open-drain pin config 2016-06-15T06:37:39+00:00 Dan O'Donovan dan@emutex.com 2016-06-10T12:23:35+00:00 ccdf81d08dbe059885d77a82adea33d0599b6421 On some CHV platforms, we need an option to configure the open-drain setting for these pins. This adds support for the PIN_CONFIG_DRIVE_PUSH_PULL and PIN_CONFIG_DRIVE_OPEN_DRAIN to disable/enable open-drain mode for a specific pin. Signed-off-by: Dan O'Donovan <dan@emutex.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
On some CHV platforms, we need an option to configure the
open-drain setting for these pins.  This adds support for the
PIN_CONFIG_DRIVE_PUSH_PULL and PIN_CONFIG_DRIVE_OPEN_DRAIN to
disable/enable open-drain mode for a specific pin.

Signed-off-by: Dan O'Donovan <dan@emutex.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: cherryview: prevent concurrent access to GPIO controllers 2016-06-15T06:37:39+00:00 Dan O'Donovan dan@emutex.com 2016-06-10T12:23:34+00:00 0bd50d719b004110e791800450ad204399100a86 Due to a silicon issue on the Atom X5-Z8000 "Cherry Trail" processor series, a common lock must be used to prevent concurrent accesses across the 4 GPIO controllers managed by this driver. See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), errata #CHT34, for further information. Cc: stable <stable@vger.kernel.org> Signed-off-by: Dan O'Donovan <dan@emutex.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Due to a silicon issue on the Atom X5-Z8000 "Cherry Trail" processor
series, a common lock must be used to prevent concurrent accesses
across the 4 GPIO controllers managed by this driver.

See Intel Atom Z8000 Processor Series Specification Update
(Rev. 005), errata #CHT34, for further information.

Cc: stable <stable@vger.kernel.org>
Signed-off-by: Dan O'Donovan <dan@emutex.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>