linux-toradex.git/drivers/pinctrl/meson/Makefile, branch master

pinctrl: Add driver support for Amlogic SoCs

2025-02-27T23:03:18+00:00

Add a new pinctrl driver for Amlogic SoCs. All future Amlogic
SoCs pinctrl drives use this, such A4, A5, S6, S7 etc. To support
new Amlogic SoCs, only need to add the corresponding dts file.

Signed-off-by: Xianwei Zhao 
Link: https://lore.kernel.org/20250212-amlogic-pinctrl-v5-3-282bc2516804@amlogic.com
Signed-off-by: Linus Walleij

pinctrl: Add driver support for Amlogic T7 SoCs

2023-09-25T13:49:18+00:00

Add a new pinctrl driver for Amlogic T7 SoCs which share
the same register layout as the previous Amlogic S4.

Signed-off-by: Huqiang Qin 
Reviewed-by: Neil Armstrong 
Reviewed-by: Andy Shevchenko 
Link: https://lore.kernel.org/r/20230922094342.637251-3-huqiang.qin@amlogic.com
Signed-off-by: Linus Walleij

pinctrl: Add driver support for Amlogic C3 SoCs

2023-07-23T19:23:27+00:00

Add a new pinctrl driver for Amlogic C3 SoCs which share
the same register layout as the previous Amlogic S4.

Signed-off-by: Huqiang Qin 
Link: https://lore.kernel.org/r/20230714122441.3098337-3-huqiang.qin@amlogic.com
Signed-off-by: Linus Walleij

pinctrl: meson: add pinctrl driver support for Meson-S4 Soc

2022-01-30T01:52:45+00:00

Add new pinctrl driver for Amlogic's Meson-S4 SoC which share the
same register layout as the previous Meson-A1.

Acked-by: Martin Blumenstingl 
Signed-off-by: Qianggui Song 
Link: https://lore.kernel.org/r/20220113031044.2665-4-qianggui.song@amlogic.com
Signed-off-by: Linus Walleij

pinctrl: meson: add pinctrl driver support for Meson-A1 SoC

2019-11-19T14:55:26+00:00

Meson A1 SoC share the same register layout of pinmux with previous
Meson-G12A, however there is difference for gpio and pin config register
in A1. The main difference is that registers before A1 are grouped by
function while those of A1 are by bank. The new register layout is as
below:

/* first bank */              /* addr */
- P_PADCTRL_GPIOP_I         base + 0x00 << 2
- P_PADCTRL_GPIOP_O         base + 0x01 << 2
- P_PADCTRL_GPIOP_OEN       base + 0x02 << 2
- P_PADCTRL_GPIOP_PULL_EN   base + 0x03 << 2
- P_PADCTRL_GPIOP_PULL_UP   base + 0x04 << 2
- P_PADCTRL_GPIOP_DS        base + 0x05 << 2

/* second bank */
- P_PADCTRL_GPIOB_I         base + 0x10 << 2
- P_PADCTRL_GPIOB_O         base + 0x11 << 2
- P_PADCTRL_GPIOB_OEN       base + 0x12 << 2
- P_PADCTRL_GPIOB_PULL_EN   base + 0x13 << 2
- P_PADCTRL_GPIOB_PULL_UP   base + 0x14 << 2
- P_PADCTRL_GPIOB_DS        base + 0x15 << 2

Each bank contains at least 6 registers to be configured, if one bank
has more than 16 gpios, an extra P_PADCTRL_GPIO[X]_DS_EXT is included.
Between two adjacent P_PADCTRL_GPIO[X]_I, there is an offset 0x10, that
is to say, for third bank, the offsets will be 0x20,0x21,0x22,0x23,0x24
,0x25 according to above register layout. For previous chips, registers
are grouped according to their functions while registers of A1 are
according to bank.Also note that there is no AO bank any more in A1.

Current Meson pinctrl driver can cover such change by using base address
of GPIO as that of drive-strength. While simply giving reg_ds = reg_pullen
make wrong value to reg_ds for Socs that do not support drive-strength
like AXG.To make things simple, add an extra dt parser function for
a1 and remain the old dt parser function for only reg parsing.

Signed-off-by: Qianggui Song 
Link: https://lore.kernel.org/r/1573819429-6937-3-git-send-email-qianggui.song@amlogic.com
Reviewed-by: Neil Armstrong 
Signed-off-by: Linus Walleij

treewide: Add SPDX license identifier - Makefile/Kconfig

2019-05-21T08:50:46+00:00

Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner 
Signed-off-by: Greg Kroah-Hartman

pinctrl: meson-g12a: add pinctrl driver support

2018-08-29T08:34:53+00:00

Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
the previous Meson-AXG SoC, both use same pinmux ops (register layout).
A new driver is needed here due to the differences in the pins.

Starting from Meson-AXG SoC, the pinctrl controller block use 4
continues register bits to specific the pin mux function, while comparing
to old generation SoC which using variable length register bits for
the pin mux definition. The new design greatly simplify the software model.

For the detail example, one 32bit register can be divided into 8 parts,
each has 4 bits whose value start from 0 - 7, each can describe one pin,
the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
the mux pin function.

Please note, the GPIOE is actually located at AO (always on) bank.

Acked-by: Martin Blumenstingl 
Signed-off-by: Xingyu Chen 
Signed-off-by: Yixun Lan 
Signed-off-by: Linus Walleij

pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC

2017-11-30T13:29:38+00:00

Add new pinctrl driver for Amlogic's Meson-AXG SoC.

Reviewed-by: Neil Armstrong 
Signed-off-by: Xingyu Chen 
Signed-off-by: Yixun Lan 
Reviewed-by: Jerome Brunet 
Signed-off-by: Linus Walleij

pinctrl: meson-axg: Introduce a pinctrl pinmux ops for Meson-AXG SoC

2017-11-30T13:28:16+00:00

The pin controller has been updated in the Amlogic Meson AXG series,
which use continuous 4-bit register to select function for each pin.
In order to support this, a new pinmux operations "meson_axg_pmx_ops"
has been added.

Reviewed-by: Neil Armstrong 
Signed-off-by: Xingyu Chen 
Signed-off-by: Yixun Lan 
Reviewed-by: Jerome Brunet 
Signed-off-by: Linus Walleij

pinctrl: meson: rework pinmux ops

2017-10-16T21:14:10+00:00

This change prepare the introduction of new meson SoC. This new SoC will
share the same gpio/pinconf registers but the pinmux part will be
different. While the format of the data associated with each pinmux group
will change, the way to handle pinmuxing will be similar.

To deal with this new situation, the meson_pmx_struture is kept but the
data associated to it is now generic. This allows to reuse the basic
functions which would otherwise be copy/pasted in each pinmux driver
(such as getting the name a count of groups and functions) Only the
functions actually using this specific data is taken out of the common
code and is handling the SoC pinmuxing

Reviewed-by: Neil Armstrong 
Reviewed-by: Kevin Hilman 
Signed-off-by: Jerome Brunet 
Signed-off-by: Linus Walleij