linux-toradex.git/drivers/pinctrl/meson, branch v4.9.87 Linux kernel for Apalis and Colibri modules pinctrl: meson-gxbb: Add missing GPIODV_18 pin entry 2017-08-16T20:43:24+00:00 Neil Armstrong narmstrong@baylibre.com 2017-05-23T14:09:19+00:00 5e5a510455323634dc3df7a2d58c985b730c31ad commit 34e61801a3b9df74b69f0e359d64a197a77dd6ac upstream. GPIODV_18 entry was missing in the original driver push. Fixes: 468c234f9ed7 ("pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
commit 34e61801a3b9df74b69f0e359d64a197a77dd6ac upstream.

GPIODV_18 entry was missing in the original driver push.

Fixes: 468c234f9ed7 ("pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
pinctrl: meson: meson8b: fix the NAND DQS pins 2017-07-12T13:01:05+00:00 Martin Blumenstingl martin.blumenstingl@googlemail.com 2017-04-01T13:59:21+00:00 a3f2e309f6540a460602639e197789e159fc0490 commit 97ba26b8a9343008504d4e3a87d212bc07b05212 upstream. The nand_groups table uses different names for the NAND DQS pins than the GROUP() definition in meson8b_cbus_groups (nand_dqs_0 vs nand_dqs0). This prevents using the NAND DQS pins in the devicetree. Fix this by ensuring that the GROUP() definition and the meson8b_cbus_groups use the same name for these pins. Fixes: 0fefcb6876d0 ("pinctrl: Add support for Meson8b") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
commit 97ba26b8a9343008504d4e3a87d212bc07b05212 upstream.

The nand_groups table uses different names for the NAND DQS pins than
the GROUP() definition in meson8b_cbus_groups (nand_dqs_0 vs nand_dqs0).
This prevents using the NAND DQS pins in the devicetree.

Fix this by ensuring that the GROUP() definition and the
meson8b_cbus_groups use the same name for these pins.

Fixes: 0fefcb6876d0 ("pinctrl: Add support for Meson8b")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
pinctrl: meson: fix gpio request disabling other modes 2017-01-19T19:18:05+00:00 Neil Armstrong narmstrong@baylibre.com 2016-12-06T14:08:16+00:00 a5209aa990423458d10849575bd768663d40bebb commit f24d311f92b516a8aadef5056424ccabb4068e7b upstream. The pinctrl_gpio_request is called with the "full" gpio number, already containing the base, then meson_pmx_request_gpio is then called with the final pin number. Remove the base addition when calling meson_pmx_disable_other_groups. Fixes: 6ac730951104 ("pinctrl: add driver for Amlogic Meson SoCs") CC: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
commit f24d311f92b516a8aadef5056424ccabb4068e7b upstream.

The pinctrl_gpio_request is called with the "full" gpio number, already
containing the base, then meson_pmx_request_gpio is then called with the
final pin number.
Remove the base addition when calling meson_pmx_disable_other_groups.

Fixes: 6ac730951104 ("pinctrl: add driver for Amlogic Meson SoCs")
CC: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Merge tag 'v4.8-rc6' into devel 2016-09-23T12:57:16+00:00 Linus Walleij linus.walleij@linaro.org 2016-09-23T12:57:16+00:00 0565f49cfe937640c2347f6d7f40ad2f4e4f088b Linux 4.8-rc6 
Linux 4.8-rc6
pinctrl: amlogic: gxbb: add i2c pins 2016-09-15T13:55:25+00:00 Jerome Brunet jbrunet@baylibre.com 2016-09-14T09:45:28+00:00 0ef823bee705a52372dfb3a9b4f3098bf9b6ae22 Add EE domains pins for the i2c devices A,B,C Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add EE domains pins for the i2c devices A,B,C

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: amlogic: gxbb: add nand pins 2016-09-15T12:14:51+00:00 Jerome Brunet jbrunet@baylibre.com 2016-09-13T15:12:22+00:00 cd1e3b01c7d30ce5e69cbd760e1edbd4d682c30d Add EE domains pins for the NAND flash controller. Even tough we have no driver for the NAND flash controller yet, we need to have these pins in pinctrl as the actual pin are shared with the spifc controller. The bootloader on the S905-P200 setup pinmux for the NAND controller so we need the kernel to properly deactivate this if necessary. Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add EE domains pins for the NAND flash controller.
Even tough we have no driver for the NAND flash controller yet, we need
to have these pins in pinctrl as the actual pin are shared with the spifc
controller. The bootloader on the S905-P200 setup pinmux for the NAND
controller so we need the kernel to properly deactivate this if necessary.

Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: amlogic: gxbb: add spi nor pins 2016-09-15T12:06:18+00:00 Jerome Brunet jbrunet@baylibre.com 2016-09-13T15:12:21+00:00 6812f19e17c1ac67774175023824bdcbe9a23674 Add EE domains pins for the SPI flash controller Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add EE domains pins for the SPI flash controller

Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson-gxbb: add the missing SDIO interrupt pin 2016-09-13T11:38:39+00:00 Martin Blumenstingl martin.blumenstingl@googlemail.com 2016-09-11T12:39:02+00:00 9b5fb0ca5d512fc28369484a4d03d376d0b17e39 This adds the SDIO interrupt pin which can be used by sd_emmc_a. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Suggested-by: Neil Armstrong <narmstrong@baylibre.com> Fixes: 29885a656511 ("pinctrl: meson-gxbb: add the pins for the SDIO/sd_emmc_a controller") Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
This adds the SDIO interrupt pin which can be used by sd_emmc_a.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Suggested-by: Neil Armstrong <narmstrong@baylibre.com>

Fixes: 29885a656511 ("pinctrl: meson-gxbb: add the pins for the
SDIO/sd_emmc_a controller")
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson-gxbb: add the pins for the SDIO/sd_emmc_a controller 2016-09-07T14:23:49+00:00 Martin Blumenstingl martin.blumenstingl@googlemail.com 2016-08-28T16:47:24+00:00 29885a656511829d5e8f69b237de47a6c23f47fa sd_emmc_a is used a controller for the SDIO modules. This adds the pin configuration for the SDIO controller. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
sd_emmc_a is used a controller for the SDIO modules. This adds the pin
configuration for the SDIO controller.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson-gxbb: add pins for PWM 2016-08-24T12:22:39+00:00 Neil Armstrong narmstrong@baylibre.com 2016-08-23T11:25:07+00:00 a9a5a443d86a7795ad00f74e6715bfca156bbb2d Add support for PWM pins, for EE and AO domains. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add support for PWM pins, for EE and AO domains.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>