linux-toradex.git/drivers/pinctrl/qcom, branch v6.0-rc1 Linux kernel for Apalis and Colibri modules Merge tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 2022-08-10T18:01:44+00:00 Linus Torvalds torvalds@linux-foundation.org 2022-08-10T18:01:44+00:00 5e2e7383b57fa03ec2b00c82bb7f49a4a707c1f7 Pull pin control updates from Linus Walleij: "Outside the pinctrl driver and DT bindings we hit some Arm DT files, patched by the maintainers. Other than that it is business as usual. Core changes: - Add PINCTRL_PINGROUP() helper macro (and use it in the AMD driver). New drivers: - Intel Meteor Lake support. - Reneasas RZ/V2M and r8a779g0 (R-Car V4H). - AXP209 variants AXP221, AXP223 and AXP809. - Qualcomm MSM8909, PM8226, PMP8074 and SM6375. - Allwinner D1. Improvements: - Proper pin multiplexing in the AMD driver. - Mediatek MT8192 can use generic drive strength and pin bias, then fixes on top plus some I2C pin group fixes. - Have the Allwinner Sunplus SP7021 use the generic DT schema and make interrupts optional. - Handle Qualcomm SC7280 ADSP. - Handle Qualcomm MSM8916 CAMSS GP clock muxing. - High impedance bias on ZynqMP. - Serialize StarFive access to MMIO. - Immutable gpiochip for BCM2835, Ingenic, Qualcomm SPMI GPIO" * tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (117 commits) dt-bindings: pinctrl: qcom,pmic-gpio: add PM8226 constraints pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM pinctrl: qcom: sm8250: Fix PDC map pinctrl: amd: Fix an unused variable dt-bindings: pinctrl: mt8186: Add and use drive-strength-microamp dt-bindings: pinctrl: mt8186: Add gpio-line-names property ARM: dts: imxrt1170-pinfunc: Add pinctrl binding header pinctrl: amd: Use unicode for debugfs output pinctrl: amd: Fix newline declaration in debugfs output pinctrl: at91: Fix typo 'the the' in comment dt-bindings: pinctrl: st,stm32: Correct 'resets' property name pinctrl: mvebu: Missing a blank line after declarations. pinctrl: qcom: Add SM6375 TLMM driver dt-bindings: pinctrl: Add DT schema for SM6375 TLMM dt-bindings: pinctrl: mt8195: Use drive-strength-microamp in examples Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable" pinctrl: imx93: Add MODULE_DEVICE_TABLE() pinctrl: sunxi: Add driver for Allwinner D1 pinctrl: sunxi: Make some layout parameters dynamic pinctrl: sunxi: Refactor register/offset calculation ... 
Pull pin control updates from Linus Walleij:
 "Outside the pinctrl driver and DT bindings we hit some Arm DT files,
  patched by the maintainers.

  Other than that it is business as usual.

  Core changes:

   - Add PINCTRL_PINGROUP() helper macro (and use it in the AMD driver).

  New drivers:

   - Intel Meteor Lake support.

   - Reneasas RZ/V2M and r8a779g0 (R-Car V4H).

   - AXP209 variants AXP221, AXP223 and AXP809.

   - Qualcomm MSM8909, PM8226, PMP8074 and SM6375.

   - Allwinner D1.

  Improvements:

   - Proper pin multiplexing in the AMD driver.

   - Mediatek MT8192 can use generic drive strength and pin bias, then
     fixes on top plus some I2C pin group fixes.

   - Have the Allwinner Sunplus SP7021 use the generic DT schema and
     make interrupts optional.

   - Handle Qualcomm SC7280 ADSP.

   - Handle Qualcomm MSM8916 CAMSS GP clock muxing.

   - High impedance bias on ZynqMP.

   - Serialize StarFive access to MMIO.

   - Immutable gpiochip for BCM2835, Ingenic, Qualcomm SPMI GPIO"

* tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (117 commits)
  dt-bindings: pinctrl: qcom,pmic-gpio: add PM8226 constraints
  pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM
  pinctrl: qcom: sm8250: Fix PDC map
  pinctrl: amd: Fix an unused variable
  dt-bindings: pinctrl: mt8186: Add and use drive-strength-microamp
  dt-bindings: pinctrl: mt8186: Add gpio-line-names property
  ARM: dts: imxrt1170-pinfunc: Add pinctrl binding header
  pinctrl: amd: Use unicode for debugfs output
  pinctrl: amd: Fix newline declaration in debugfs output
  pinctrl: at91: Fix typo 'the the' in comment
  dt-bindings: pinctrl: st,stm32: Correct 'resets' property name
  pinctrl: mvebu: Missing a blank line after declarations.
  pinctrl: qcom: Add SM6375 TLMM driver
  dt-bindings: pinctrl: Add DT schema for SM6375 TLMM
  dt-bindings: pinctrl: mt8195: Use drive-strength-microamp in examples
  Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable"
  pinctrl: imx93: Add MODULE_DEVICE_TABLE()
  pinctrl: sunxi: Add driver for Allwinner D1
  pinctrl: sunxi: Make some layout parameters dynamic
  pinctrl: sunxi: Refactor register/offset calculation
  ...
pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM 2022-08-03T18:31:14+00:00 John Garry john.garry@huawei.com 2022-07-26T10:02:44+00:00 9a206bca238177f7fa09fef6735aab7d5d3b2b19 All the many other configs depend on config PINCTRL_MSM, yet for config PINCTRL_SM8450 we select config PINCTRL_MSM. Make config PINCTRL_SM8450 depend on PINCTRL_MSM to be consistent with the rest. Signed-off-by: John Garry <john.garry@huawei.com> Suggested-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/1658829764-124936-1-git-send-email-john.garry@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
All the many other configs depend on config PINCTRL_MSM, yet for config
PINCTRL_SM8450 we select config PINCTRL_MSM. Make config PINCTRL_SM8450
depend on PINCTRL_MSM to be consistent with the rest.

Signed-off-by: John Garry <john.garry@huawei.com>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/1658829764-124936-1-git-send-email-john.garry@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: qcom: sm8250: Fix PDC map 2022-08-03T18:20:56+00:00 Jianhua Lu lujianhua000@gmail.com 2022-08-03T01:56:45+00:00 4b759ca15a4914f96ea204ea9200ceeb01d70666 Fix the PDC mapping for SM8250, gpio39 is mapped to irq73(not irq37). Fixes: b41efeed507a("pinctrl: qcom: sm8250: Specify PDC map.") Signed-off-by: Jianhua Lu <lujianhua000@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20220803015645.22388-1-lujianhua000@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Fix the PDC mapping for SM8250, gpio39 is mapped to irq73(not irq37).

Fixes: b41efeed507a("pinctrl: qcom: sm8250: Specify PDC map.")
Signed-off-by: Jianhua Lu <lujianhua000@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20220803015645.22388-1-lujianhua000@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: qcom: Add SM6375 TLMM driver 2022-07-26T07:28:53+00:00 Konrad Dybcio konrad.dybcio@somainline.org 2022-07-16T19:29:00+00:00 f1a5013f9193989bc0b4f58f78fc3f5cdda324e4 Add a driver to control the TLMM block on SM6375. This is an adapted version of msm-5.4's pinctrl-blair driver. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20220716192900.454653-2-konrad.dybcio@somainline.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add a driver to control the TLMM block on SM6375. This is an adapted
version of msm-5.4's pinctrl-blair driver.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20220716192900.454653-2-konrad.dybcio@somainline.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable" 2022-07-18T09:58:09+00:00 Linus Walleij linus.walleij@linaro.org 2022-07-18T09:58:09+00:00 4a2d4e2df5a58c5a1feb6a46ba276c373ae0f17d This reverts commit 7542766e78fc374d81d8c2db214c4b4308645277. It was noted during follow-up that the approach is incorrect. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
This reverts commit 7542766e78fc374d81d8c2db214c4b4308645277.

It was noted during follow-up that the approach is incorrect.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: qcom-pmic-gpio: add support for PMP8074 2022-07-18T09:38:37+00:00 Robert Marko robimarko@gmail.com 2022-07-11T20:34:05+00:00 6cd81a86ff11ae2cc4c3569293e2ddceadcbdc77 PMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12. Signed-off-by: Robert Marko <robimarko@gmail.com> Link: https://lore.kernel.org/r/20220711203408.2949888-4-robimarko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
PMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20220711203408.2949888-4-robimarko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: qcom: spmi-gpio: Add pm8226 compatibility 2022-07-18T09:38:37+00:00 Dominik Kobinski dominikkobinski314@gmail.com 2021-11-25T21:53:10+00:00 eebe11b5bbec0cc34cb27176f537098ec205f8bc Add support for pm8226 SPMI GPIOs. The PMIC features 8 GPIOs, with no holes inbetween. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Suggested-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Signed-off-by: Dominik Kobinski <dominikkobinski314@gmail.com> Link: https://lore.kernel.org/r/20211125215310.62371-1-dominikkobinski314@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add support for pm8226 SPMI GPIOs. The PMIC features
8 GPIOs, with no holes inbetween.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Suggested-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Signed-off-by: Dominik Kobinski <dominikkobinski314@gmail.com>
Link: https://lore.kernel.org/r/20211125215310.62371-1-dominikkobinski314@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: qcom: Add pinctrl driver for MSM8909 2022-07-11T08:26:52+00:00 Stephan Gerhold stephan.gerhold@kernkonzept.com 2022-06-28T14:55:02+00:00 4528a0cf793d6f174b58920459fe2854378146a9 Make it possible to control pins using the TLMM block in the MSM8909 SoC by adding the necessary definitions for GPIOs, groups and functions. The driver is originally taken from the msm-4.9 release [1] from Qualcomm, but cleaned up significantly with several fixes and clarifications. [1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.7-22500-8x09.0/drivers/pinctrl/qcom/pinctrl-msm8909.c Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220628145502.4158234-3-stephan.gerhold@kernkonzept.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Make it possible to control pins using the TLMM block in the MSM8909 SoC
by adding the necessary definitions for GPIOs, groups and functions.

The driver is originally taken from the msm-4.9 release [1] from Qualcomm,
but cleaned up significantly with several fixes and clarifications.

[1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.7-22500-8x09.0/drivers/pinctrl/qcom/pinctrl-msm8909.c

Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220628145502.4158234-3-stephan.gerhold@kernkonzept.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
gpio: Remove dynamic allocation from populate_parent_alloc_arg() 2022-07-10T08:30:00+00:00 Marc Zyngier maz@kernel.org 2022-07-07T18:23:09+00:00 91a29af413def677495e447fb9a06957ebc8bed5 The gpiolib is unique in the way it uses intermediate fwspecs when feeding an interrupt specifier to the parent domain, as it relies on the populate_parent_alloc_arg() callback to perform a dynamic allocation. This is pretty inefficient (we free the structure almost immediately), and the only reason this isn't a stack allocation is that our ThunderX friend uses MSIs rather than a FW-constructed structure. Let's solve it by providing a new type composed of the union of a struct irq_fwspec and a msi_info_t, which satisfies both requirements. This allows us to use a stack allocation, and we can move the handful of users to this new scheme. Also perform some additional cleanup, such as getting rid of the stub versions of the irq_domain_translate_*cell helpers, which are never used when CONFIG_IRQ_DOMAIN_HIERARCHY isn't selected. Tested on a Tegra186. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: Daniel Palmer <daniel@thingy.jp> Cc: Romain Perier <romain.perier@gmail.com> Cc: Bartosz Golaszewski <brgl@bgdev.pl> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Robert Richter <rric@kernel.org> Cc: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Bartosz Golaszewski <brgl@bgdev.pl> Link: https://lore.kernel.org/r/20220707182314.66610-2-prabhakar.mahadev-lad.rj@bp.renesas.com 
The gpiolib is unique in the way it uses intermediate fwspecs
when feeding an interrupt specifier to the parent domain, as it
relies on the populate_parent_alloc_arg() callback to perform
a dynamic allocation.

This is pretty inefficient (we free the structure almost immediately),
and the only reason this isn't a stack allocation is that our
ThunderX friend uses MSIs rather than a FW-constructed structure.

Let's solve it by providing a new type composed of the union
of a struct irq_fwspec and a msi_info_t, which satisfies both
requirements. This allows us to use a stack allocation, and we
can move the handful of users to this new scheme.

Also perform some additional cleanup, such as getting rid of the
stub versions of the irq_domain_translate_*cell helpers, which
are never used when CONFIG_IRQ_DOMAIN_HIERARCHY isn't selected.

Tested on a Tegra186.

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: Daniel Palmer <daniel@thingy.jp>
Cc: Romain Perier <romain.perier@gmail.com>
Cc: Bartosz Golaszewski <brgl@bgdev.pl>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Robert Richter <rric@kernel.org>
Cc: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Bartosz Golaszewski <brgl@bgdev.pl>
Link: https://lore.kernel.org/r/20220707182314.66610-2-prabhakar.mahadev-lad.rj@bp.renesas.com
pinctrl: qcom: spmi-gpio: make the irqchip immutable 2022-07-09T23:04:51+00:00 Robert Marko robimarko@gmail.com 2022-06-24T19:51:12+00:00 7542766e78fc374d81d8c2db214c4b4308645277 Commit 6c846d026d49 ("gpio: Don't fiddle with irqchips marked as immutable") added a warning to indicate if the gpiolib is altering the internals of irqchips. Following this change the following warning is now observed for the SPMI PMIC pinctrl driver: gpio gpiochip1: (200f000.spmi:pmic@0:gpio@c000): not an immutable chip, please consider fixing it! Fix this by making the irqchip in the SPMI PMIC pinctrl driver immutable. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220624195112.894916-1-robimarko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Commit 6c846d026d49 ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips.

Following this change the following warning is now observed for the SPMI
PMIC pinctrl driver:
gpio gpiochip1: (200f000.spmi:pmic@0:gpio@c000): not an immutable chip, please consider fixing it!

Fix this by making the irqchip in the SPMI PMIC pinctrl driver immutable.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20220624195112.894916-1-robimarko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>