linux-toradex.git/drivers/pinctrl/qcom, branch v6.12-rc4

pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now

2024-09-02T09:07:48+00:00

On X1E80100, GPIO interrupts for wakeup-capable pins have been broken since
the introduction of the pinctrl driver. This prevents keyboard and touchpad
from working on most of the X1E laptops. So far we have worked around this
by manually building a kernel with the "wakeup-parent" removed from the
pinctrl node in the device tree, but we cannot expect all users to do that.

Implement a similar workaround in the driver by clearing the wakeirq_map
for X1E80100. This avoids using the PDC wakeup parent for all GPIOs
and handles the interrupts directly in the pinctrl driver instead.

The PDC driver needs additional changes to support X1E80100 properly.
Adding a workaround separately first allows to land the necessary PDC
changes through the normal release cycle, while still solving the more
critical problem with keyboard and touchpad on the current stable kernel
versions. Bypassing the PDC is enough for now, because we have not yet
enabled the deep idle states where using the PDC becomes necessary.

Cc: stable@vger.kernel.org
Fixes: 05e4941d97ef ("pinctrl: qcom: Add X1E80100 pinctrl driver")
Signed-off-by: Stephan Gerhold 
Reviewed-by: Johan Hovold 
Tested-by: Johan Hovold 
Reviewed-by: Konrad Dybcio 
Reviewed-by: Abel Vesa 
Link: https://lore.kernel.org/20240830-x1e80100-bypass-pdc-v1-1-d4c00be0c3e3@linaro.org
Signed-off-by: Linus Walleij

pinctrl: qcom: x1e80100: Fix special pin offsets

2024-08-23T16:13:45+00:00

Remove the erroneus 0x100000 offset to prevent the boards from crashing
on pin state setting, as well as for the intended state changes to take
effect.

Fixes: 05e4941d97ef ("pinctrl: qcom: Add X1E80100 pinctrl driver")
Signed-off-by: Konrad Dybcio 
Reviewed-by: Abel Vesa 
Reviewed-by: Bjorn Andersson 
Link: https://lore.kernel.org/20240809-topic-h_sdc-v1-1-bb421532c531@quicinc.com
Signed-off-by: Linus Walleij

pinctrl: qcom: x1e80100: Update PDC hwirq map

2024-08-05T07:29:59+00:00

The current map seems to be out of sync (and includes a duplicate entry
for GPIO193..).

Replace it with the map present in shipping devices' ACPI tables.

This new one seems more complete, as it e.g. contains GPIO145 (PCIE6a
WAKE#)

Fixes: 05e4941d97ef ("pinctrl: qcom: Add X1E80100 pinctrl driver")
Signed-off-by: Konrad Dybcio 
Reviewed-by: Abel Vesa 
Reviewed-by: Rajendra Nayak 
Link: https://lore.kernel.org/20240711-topic-x1e_pdc_tlmm-v1-1-e278b249d793@linaro.org
Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2024-07-21T17:25:59+00:00

Pull pin control updates from Linus Walleij:
 "Some new drivers is the main part, the rest is cleanups and nonurgent
  fixes.

  Nothing much special about this, no core changes this time.

  New drivers:

   - Renesas RZ/V2H(P) SoC

   - NXP Freescale i.MX91 SoC

   - Nuvoton MA35D1 SoC

   - Qualcomm PMC8380, SM4250, SM4250 LPI

  Enhancements:

   - A slew of scoped-based simplifications of of_node_put()"

* tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits)
  pinctrl: renesas: rzg2l: Support output enable on RZ/G2L
  pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions
  pinctrl: renesas: rzg2l: Clarify OEN read/write support
  dt-bindings: pinctrl: pinctrl-single: Fix pinctrl-single,gpio-range description
  dt-bindings: pinctrl: npcm8xx: add missing pin group and mux function
  dt-bindings: pinctrl: pinctrl-single: fix schmitt related properties
  pinctrl: freescale: Use scope based of_node_put() cleanups
  pinctrl: equilibrium: Use scope based of_node_put() cleanups
  pinctrl: ti: iodelay: Use scope based of_node_put() cleanups
  pinctrl: qcom: lpass-lpi: increase MAX_NR_GPIO to 32
  pinctrl: cy8c95x0: Update cache modification
  pinctrl: cy8c95x0: Use cleanup.h
  pinctrl: renesas: r8a779h0: Remove unneeded separators
  pinctrl: renesas: r8a779g0: Add INTC-EX pins, groups, and function
  pinctrl: renesas: r8a779g0: Remove unneeded separators
  pinctrl: renesas: r8a779h0: Add AVB MII pins and groups
  pinctrl: renesas: r8a779g0: Fix TPU suffixes
  pinctrl: renesas: r8a779g0: Fix TCLK suffixes
  pinctrl: renesas: r8a779g0: FIX PWM suffixes
  pinctrl: renesas: r8a779g0: Fix IRQ suffixes
  ...

pinctrl: qcom: lpass-lpi: increase MAX_NR_GPIO to 32

2024-07-03T12:31:09+00:00

Account for more than only 23 GPIOs in LPASS Low Power Island pinctrl
generic driver. The previous value 23 was chosen to satisfy existing
SoC-specific drivers. However SM4250 LPI pinctrl uses more than 23 GPIOs
and its probe routine fails on:

        if (WARN_ON(data->npins > MAX_NR_GPIO))
                return -EINVAL;

with the following message:

[   10.709014] ------------[ cut here ]------------
[   10.719085] WARNING: CPU: 1 PID: 56 at
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c:446
lpi_pinctrl_probe+0x308/0x388 [pinctrl_lpass_lpi]
[   10.719108] Modules linked in: [...]
[   10.719238] CPU: 1 PID: 56 Comm: kworker/u33:0 Not tainted
6.10.0-rc2-00012-ge45ddb1f8d34-dirty #7
[   10.719245] Hardware name: Qualcomm Technologies, Inc. QRB4210 RB2 (DT)
[   10.719250] Workqueue: events_unbound deferred_probe_work_func
[   10.719265] pstate: 20000005 (nzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[   10.719271] pc : lpi_pinctrl_probe+0x308/0x388 [pinctrl_lpass_lpi]
[   10.719278] lr : lpi_pinctrl_probe+0x44/0x388 [pinctrl_lpass_lpi]
        ...
[   10.719357] Call trace:
[   10.719361]  lpi_pinctrl_probe+0x308/0x388 [pinctrl_lpass_lpi]
[   10.719369]  platform_probe+0x68/0xc4
[   10.719378]  really_probe+0xbc/0x29c
[   10.719384]  __driver_probe_device+0x78/0x12c
[   10.719390]  driver_probe_device+0xd8/0x15c
[   10.719395]  __device_attach_driver+0xb8/0x134
[   10.719401]  bus_for_each_drv+0x88/0xe8
[   10.719407]  __device_attach+0xa0/0x190
[   10.719412]  device_initial_probe+0x14/0x20
[   10.719418]  bus_probe_device+0xac/0xb0
[   10.719423]  deferred_probe_work_func+0x88/0xc0
[   10.719429]  process_one_work+0x150/0x294
[   10.719439]  worker_thread+0x2f8/0x408
[   10.719445]  kthread+0x110/0x114
[   10.719452]  ret_from_fork+0x10/0x20
[   10.719459] ---[ end trace 0000000000000000 ]---
[   10.719589] qcom-sm4250-lpass-lpi-pinctrl a7c0000.pinctrl: probe
with driver qcom-sm4250-lpass-lpi-pinctrl failed with error -22

Fixes: c2e5a25e8d88 ("pinctrl: qcom: Introduce SM4250 LPI pinctrl driver")
Signed-off-by: Alexey Klimov 
Reviewed-by: Dmitry Baryshkov 
Link: https://lore.kernel.org/20240627003654.242870-1-alexey.klimov@linaro.org
Signed-off-by: Linus Walleij

pinctrl: qcom: Introduce SM4250 LPI pinctrl driver

2024-06-26T10:41:07+00:00

Add support for the pin controller block on SM4250 Low Power Island.

Signed-off-by: Srinivas Kandagatla 
Reviewed-by: Krzysztof Kozlowski 
Reviewed-by: Dmitry Baryshkov 
Link: https://lore.kernel.org/20240612-sm4250-lpi-v4-2-a0342e47e21b@linaro.org
Signed-off-by: Linus Walleij

pinctrl: qcom: sdm670: add pdc wakeirq map

2024-06-17T07:25:45+00:00

The PDC was hooked up as a wakeup parent in the DTS in
commit 71f080633d1e ("arm64: dts: qcom: sdm670: Hook up PDC as
wakeup-parent of TLMM"), but the wakeirq mapping was not defined so it
had no effect. Add the mapping for wakeup interrupts on the PDC to their
corresponding pins.

Configuring a pin IRQ as dual-edge would break it unless the
wakeirq_dual_edge_errata flag is set.

Signed-off-by: Richard Acayan 
Link: https://lore.kernel.org/r/20240523230619.256882-2-mailingradian@gmail.com
Signed-off-by: Linus Walleij

pinctrl: qcom: spmi: Add PMC8380

2024-06-17T07:22:41+00:00

PMC8380 is a new chip, featuring 10 GPIOs. Describe it.

Signed-off-by: Konrad Dybcio 
Reviewed-by: Dmitry Baryshkov 
Reviewed-by: Neil Armstrong 
Link: https://lore.kernel.org/r/20240525-topic-pmc8380_gpio-v2-2-2de50cb28ac1@linaro.org
Signed-off-by: Linus Walleij

pinctrl: qcom: spmi-gpio: drop broken pm8008 support

2024-06-17T07:16:54+00:00

The SPMI GPIO driver assumes that the parent device is an SPMI device
and accesses random data when backcasting the parent struct device
pointer for non-SPMI devices.

Fortunately this does not seem to cause any issues currently when the
parent device is an I2C client like the PM8008, but this could change if
the structures are reorganised (e.g. using structure randomisation).

Notably the interrupt implementation is also broken for non-SPMI devices.

Also note that the two GPIO pins on PM8008 are used for interrupts and
reset so their practical use should be limited.

Drop the broken GPIO support for PM8008 for now.

Fixes: ea119e5a482a ("pinctrl: qcom-pmic-gpio: Add support for pm8008")
Cc: stable@vger.kernel.org	# 5.13
Reviewed-by: Bryan O'Donoghue 
Reviewed-by: Stephen Boyd 
Signed-off-by: Johan Hovold 
Link: https://lore.kernel.org/r/20240529162958.18081-9-johan+linaro@kernel.org
Signed-off-by: Linus Walleij

pinctrl: qcom: pinctrl-sm7150: Fix sdc1 and ufs special pins regs

2024-05-03T07:55:04+00:00

SDC1 and UFS_RESET special pins are located in the west memory bank.

SDC1 have address 0x359a000:
0x3500000 (TLMM BASE) + 0x0 (WEST) + 0x9a000 (SDC1_OFFSET) = 0x359a000

UFS_RESET have address 0x359f000:
0x3500000 (TLMM BASE) + 0x0 (WEST) + 0x9f000 (UFS_OFFSET) = 0x359a000

Fixes: b915395c9e04 ("pinctrl: qcom: Add SM7150 pinctrl driver")
Signed-off-by: Danila Tikhonov 
Message-ID: <20240423203245.188480-1-danila@jiaxyga.com>
Signed-off-by: Linus Walleij