linux-toradex.git/drivers/pinctrl/sh-pfc, branch v4.10

pinctrl: sh-pfc: r8a7795: Add group for QSPI0 and QSPI1 pins

2016-11-16T09:29:14+00:00

Group the QSPI0 and QSPI1 pins into similar groups found in other sh-pfc
drivers. The pins can not be muxed between functions other than QSPI,
but their drive strength can be controlled.

Signed-off-by: Niklas Söderlund 
Signed-off-by: Geert Uytterhoeven

pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pins

2016-11-16T09:29:13+00:00

Group the AVB pins into similar groups found in other sh-pfc drivers.
The pins can not be muxed between functions other then AVB but their
drive strength can be controlled.

The group avb_mdc containing ADV_MDC and ADV_MDIO are on other SoCs
called avb_mdio. In pfc-r8a7795 the avb_mdc group already existed and
is in use in DT. Therefore add the ADV_MDIO pin to the existing group
instead of renaming it.

Signed-off-by: Niklas Söderlund 
Signed-off-by: Geert Uytterhoeven

pinctrl: sh-pfc: r8a7795: Support none GPIO pins with configurable drive-strength

2016-11-16T09:29:12+00:00

There are pins on the r8a7795 which are not part of a GPIO bank nor
can be muxed between different functions. They do however allow for the
drive-strength to be configured. Add those pins to the list of pins and
to the drive-strength configuration registers.

The pins can now be referred to in DT by function names and their
drive-strength modified.

Signed-off-by: Niklas Söderlund 
Signed-off-by: Geert Uytterhoeven

pinctrl: sh-pfc: Support named pins with custom configuration

2016-11-16T09:29:12+00:00

Pins not associated with a GPIO port can still have other configuration
parameters. Add a new macro SH_PFC_PIN_NAMED_CFG which allows for named
pins to be declared with a set of configurations. The new macro is an
modification of SH_PFC_PIN_NAMED to allow for optional configuration to
be assigned.

The flag SH_PFC_PIN_CFG_NO_GPIO is still enforced as this should only be
used to define pins not associated with a GPIO port.

Signed-off-by: Niklas Söderlund 
Acked-by: Laurent Pinchart 
Signed-off-by: Geert Uytterhoeven

pinctrl: sh-pfc: r8a7778: Use lookup function for bias data

2016-11-16T09:29:11+00:00

Change the data structure and use the generic sh_pfc_pin_to_bias_info()
function to get the register offset and bit information.

Suggested-by: Laurent Pinchart 
Signed-off-by: Niklas Söderlund 
Reviewed-by: Laurent Pinchart 
Signed-off-by: Geert Uytterhoeven

pinctrl: sh-pfc: r8a7795: Use lookup function for bias data

2016-11-16T09:29:10+00:00

There is a bug in the r8a7795 bias code where a WARN() is trigged
anytime a pin from PUEN0/PUD0 is accessed.

 # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins

 WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8
 [..]
 Call trace:
 [] r8a7795_pinmux_get_bias+0xbc/0xc8
 [] sh_pfc_pinconf_get+0x194/0x270
 [] pin_config_get_for_pin+0x20/0x30
 [] pinconf_generic_dump_one+0x168/0x188
 [] pinconf_generic_dump_pins+0x5c/0x98
 [] pinconf_pins_show+0xc8/0x128
 [] seq_read+0x16c/0x420
 [] full_proxy_read+0x58/0x88
 [] __vfs_read+0x1c/0xf8
 [] vfs_read+0x84/0x148
 [] SyS_read+0x44/0xa0
 [] __sys_trace_return+0x0/0x4

This is due to the WARN() check if the reg field of the pullups struct
is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
registers since PU0 is defined as 0. Change the data structure and use
the generic sh_pfc_pin_to_bias_info() function to get the register
offset and bit information.

Fixes: 560655247b627ac7 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf support")
Signed-off-by: Niklas Söderlund 
Reviewed-by: Laurent Pinchart 
Signed-off-by: Geert Uytterhoeven

pinctrl: sh-pfc: r8a7795: Simplify get bias logic

2016-11-16T09:28:58+00:00

The last else statement is missing braces, and the indentation level can
be reduced.

Suggested-by: Laurent Pinchart 
Signed-off-by: Niklas Söderlund 
Reviewed-by: Laurent Pinchart 
Signed-off-by: Geert Uytterhoeven

pinctrl: sh-pfc: Add helper to handle bias lookup table

2016-11-15T10:01:09+00:00

On some SoC there are no simple mapping of pins to bias register bits
and a lookup table is needed. This logic is already implemented in some
SoC specific drivers that could benefit from a generic implementation.

Add helpers to deal with the lookup which later can be used by the SoC
specific drivers. The logic used to lookup are different from the one it
aims to replace, this is intentional. This new method reduces the memory
consumption at the cost of increased CPU usage and fix a bug where a
WARN() would incorrectly be triggered if the register offset is 0.

Signed-off-by: Niklas Söderlund 
Reviewed-by: Laurent Pinchart 
Signed-off-by: Geert Uytterhoeven

pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE

2016-11-15T10:01:09+00:00

Always stating PIN_CONFIG_BIAS_DISABLE is supported gives untrue output
when examining /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins if
the operation get_bias() is implemented but the pin is not handled by
the get_bias() implementation. In that case the output will state that
"input bias disabled" indicating that this pin has bias control
support.

Make support for PIN_CONFIG_BIAS_DISABLE depend on that the pin either
supports SH_PFC_PIN_CFG_PULL_UP or SH_PFC_PIN_CFG_PULL_DOWN. This also
solves the issue where SoC specific implementations print error messages
if their particular implementation of {set,get}_bias() is called with a
pin it does not know about.

Signed-off-by: Niklas Söderlund 
Acked-by: Laurent Pinchart 
Signed-off-by: Geert Uytterhoeven

pinctrl: sh-pfc: r8a7796: Add DU support

2016-11-15T10:01:08+00:00

Only the DU parallel RGB output signals are included, HDMI and TCON pins
will be added in separate groups. Based on a similar patch from Laurent
Pinchart for the r8a7795 PFC driver.

Signed-off-by: Niklas Söderlund 
Reviewed-by: Laurent Pinchart 
Signed-off-by: Geert Uytterhoeven