linux-toradex.git/drivers/pinctrl/sh-pfc, branch v4.12-rc1

Merge tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2017-05-03T00:59:33+00:00

Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.12 cycle.

The extra week before the merge window actually resulted in some of
the type of fixes that usually arrive after the merge window already
starting to trickle in from eager developers using -next, I'm
impressed.

I have recruited a Samsung subsubsystem maintainer (Krzysztof) to deal
with the onset of Samsung patches. It works great.

Apart from that it is a boring round, just incremental updates and
fixes all over the place, no serious core changes or anything exciting
like that. The most pleasing to see is Julia Cartwrights work to audit
the irqchip-providing drivers for realtime locking compliance. It's
one of those "I should really get around to looking into that" things
that have been on my TODO list since forever.

Summary:

Core changes:

- add bi-directional and output-enable pin configurations to the
generic bindings and generic pin controlling core.

New drivers or subdrivers:

- Armada 37xx SoC pin controller and GPIO support.

- Axis ARTPEC-6 SoC pin controller support.

- AllWinner A64 R_PIO controller support, and opening up the
AllWinner sunxi driver for ARM64 use.

- Rockchip RK3328 support.

- Renesas R-Car H3 ES2.0 support.

- STM32F469 support in the STM32 driver.

- Aspeed G4 and G5 pin controller support.

Improvements:

- a whole slew of realtime improvements to drivers implementing
irqchips: BCM, AMD, SiRF, sunxi, rockchip.

- switch meson driver to get the GPIO ranges from the device tree.

- input schmitt trigger support on the Rockchip driver.

- enable the sunxi (AllWinner) driver to also be used on ARM64
silicon.

- name the Qualcomm QDF2xxx GPIO lines.

- support GMMR GPIO regions on the Intel Cherryview. This fixes a
serialization problem on these platforms.

- pad retention support for the Samsung Exynos 5433.

- handle suspend-to-ram in the AT91-pio4 driver.

- pin configuration support in the Aspeed driver.

Cleanups:

- the final name of Rockchip RK1108 was RV1108 so rename the driver
and variables to stay consistent"

* tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
pinctrl: mediatek: Add missing pinctrl bindings for mt7623
pinctrl: artpec6: Fix return value check in artpec6_pmx_probe()
pinctrl: artpec6: Remove .owner field for driver
pinctrl: tegra: xusb: Silence sparse warnings
ARM: at91/at91-pinctrl documentation: fix spelling mistake: "contoller" -> "controller"
pinctrl: make artpec6 explicitly non-modular
pinctrl: aspeed: g5: Add pinconf support
pinctrl: aspeed: g4: Add pinconf support
pinctrl: aspeed: Add core pinconf support
pinctrl: aspeed: Document pinconf in devicetree bindings
pinctrl: Add st,stm32f469-pinctrl compatible to stm32-pinctrl
pinctrl: stm32: Add STM32F469 MCU support
Documentation: dt: Remove ngpios from stm32-pinctrl binding
pinctrl: stm32: replace device_initcall() with arch_initcall()
pinctrl: stm32: add possibility to use gpio-ranges to declare bank range
pinctrl: armada-37xx: Add gpio support
pinctrl: armada-37xx: Add pin controller support for Armada 37xx
pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
pinctrl: core: Make pinctrl_init_controller() static
pinctrl: generic: Add bi-directional and output-enable
...

pinctrl: core: Fix pinctrl_register_and_init() with pinctrl_enable()

2017-04-06T23:08:08+00:00

Recent pinctrl changes to allow dynamic allocation of pins exposed one
more issue with the pinctrl pins claimed early by the controller itself.
This caused a regression for IMX6 pinctrl hogs.

Before enabling the pin controller driver we need to wait until it has
been properly initialized, then claim the hogs, and only then enable it.

To fix the regression, split the code into pinctrl_claim_hogs() and
pinctrl_enable(). And then let's require that pinctrl_enable() is always
called by the pin controller driver when ready after calling
pinctrl_register_and_init().

Depends-on: 950b0d91dc10 ("pinctrl: core: Fix regression caused by delayed
work for hogs")
Fixes: df61b366af26 ("pinctrl: core: Use delayed work for hogs")
Fixes: e566fc11ea76 ("pinctrl: imx: use generic pinctrl helpers for
managing groups")
Cc: Haojian Zhuang 
Cc: Masahiro Yamada 
Cc: Mika Penttilä 
Cc: Mika Westerberg 
Cc: Nishanth Menon 
Cc: Shawn Guo 
Cc: Stefan Agner 
Tested-by: Geert Uytterhoeven 
Tested-by: Gary Bisson 
Tested-by: Fabio Estevam 
Signed-off-by: Tony Lindgren 
Signed-off-by: Linus Walleij

pinctrl: sh-pfc: r8a7794: Swap ATA signals

2017-04-05T07:41:29+00:00

All R8A7794 manuals I have here (0.50 and 1.10) agree that the PFC driver
has ATAG0# and ATAWR0# signals in IPSR12 swapped -- fix this.

Fixes: 43c4436e2f18 ("pinctrl: sh-pfc: add R8A7794 PFC support")
Signed-off-by: Sergei Shtylyov 
Signed-off-by: Geert Uytterhoeven

pinctrl: sh-pfc: r8a7791: Fix IPSR comment typos

2017-04-04T07:22:27+00:00

The IPSR field names in the comments have been fat-fingered in a couple
places --  fix those silly typos...

Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support")
Signed-off-by: Sergei Shtylyov 
Signed-off-by: Geert Uytterhoeven

pinctrl: sh-pfc: r8a7791: Fix SCIF2 pinmux data

2017-04-04T07:22:26+00:00

PINMUX_IPSR_MSEL() macro invocation for the TX2 signal has apparently wrong
1st argument -- most probably a result of cut&paste programming...

Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support")
Signed-off-by: Sergei Shtylyov 
Signed-off-by: Geert Uytterhoeven

pinctrl: sh-pfc: r8a7791: Add missing DVC_MUTE signal

2017-04-04T07:22:26+00:00

The R8A7791 PFC driver  was apparently based on the preliminary revisions
of  the user's  manual, which  omitted the DVC_MUTE signal  altogether in
the PFC section. The modern manual has the signal described,  so just add
the necassary data to the driver...

Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support")
Signed-off-by: Sergei Shtylyov 
Signed-off-by: Geert Uytterhoeven

pinctrl: sh-pfc: r8a7791: Add missing HSCIF1 pinmux data

2017-04-04T07:22:25+00:00

The R8A7791 PFC driver  was apparently based on the preliminary revisions
of  the  user's manual, which  omitted the HSCIF1 group E signals in  the
IPSR4 register description. This would cause HSCIF1's probe  to fail with
the messages like below:

sh-pfc e6060000.pfc: cannot locate data/mark enum_id for mark 1989
sh-sci e62c8000.serial: Error applying setting, reverse things back
sh-sci: probe of e62c8000.serial failed with error -22

Add the neceassary PINMUX_IPSR_MSEL() invocations for the HSCK1_E,
HCTS1#_E, and HRTS1#_E signals...

Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support")
Signed-off-by: Sergei Shtylyov 
Signed-off-by: Geert Uytterhoeven

pinctrl: sh-pfc: r8a7795: Add SCIF_CLK support

2017-03-30T11:43:55+00:00

Add pins, groups, and a function for SCIF_CLK on R-Car H3 ES2.0.
SCIF_CLK is the external clock source for the Baud Rate Generator for
External Clock (BRG) on (H)SCIF serial ports.

Extracted from a big patch in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven 
Cc: Takeshi Kihara

pinctrl: sh-pfc: r8a7795: Add SCIF support

2017-03-30T11:43:51+00:00

Add pins, groups, and functions for all SCIF serial ports on R-Car H3
ES2.0.

Extracted from a big patch in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven 
Cc: Takeshi Kihara

pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0

2017-03-30T11:43:45+00:00

The Pin Function Controller module in the R-Car H3 ES2.0 differs from
ES1.x in many ways.

The goal is twofold:
  1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
     for now,
  2. Make it clear which code supports ES1.x, so it can easily be
     identified and removed later, when production SoCs are deemed
     ubiquitous.

Hence this patch:
  1. Extracts the support for R-Car H3 ES1.x into a separate file, as
     the differences are quite large,
  2. Adds code for detecting the SoC revision at runtime using the new
     soc_device_match() API, and selecting pinctrl tables for the actual
     SoC revision,
  3. Replaces the core register and bitfield definitions by their
     counterparts for R-Car H3 ES2.0.

The addition of pins, groups, and functions for the various on-chip
devices is left to subsequent patches.

The R-Car H3 ES2.0 register and bitfield definitions were extracted from
a patch in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven 
Cc: Takeshi Kihara