linux-toradex.git/drivers/pinctrl/sunxi/Makefile, branch v4.10

pinctrl: sunxi: Add GR8 controller support

2016-09-07T19:15:49+00:00

Just like the other member of the sunxi family, let's add a pinctrl table
for the muxing options.

Signed-off-by: Mylène Josserand 
Signed-off-by: Maxime Ripard 
Acked-by: Chen-Yu Tsai 
Signed-off-by: Linus Walleij

drivers: pinctrl: add driver for Allwinner A64 SoC

2016-03-11T15:46:27+00:00

Based on the Allwinner A64 user manual and on the previous sunxi
pinctrl drivers this introduces the pin multiplex assignments for
the ARMv8 Allwinner A64 SoC.
Port A is apparently used for the fixed function DRAM controller, so
the ports start at B here (the manual mentions "n from 1 to 7", so
not starting at 0).

Signed-off-by: Andre Przywara 
Acked-by: Rob Herring 
Acked-by: Maxime Ripard 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Add H3 R_PIO controller support

2016-02-11T13:29:24+00:00

H3 has additional PIO controller similar to what we can find on A23.
It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.

Signed-off-by: Krzysztof Adamski 
Acked-by: Maxime Ripard 
Signed-off-by: Linus Walleij

pinctrl: sunxi: guard sub-directory with CONFIG_PINCTRL_SUNXI

2016-01-28T13:25:50+00:00

CONFIG_PINCTRL_SUNXI is more suitable than CONFIG_ARCH_SUNXI
to guard the drivers/pinctrl/sunxi/ directory.
(I renamed CONFIG_PINCTRL_SUNXI_COMMON to CONFIG_PINCTRL_SUNXI.)

Signed-off-by: Masahiro Yamada 
Acked-by: Maxime Ripard 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Add A80 special pin controller

2015-12-22T09:28:11+00:00

Like the previous designs, the A80 has a special pin controller for the
critical pins, like the PMIC bus.

Add a driver for this controller.

Signed-off-by: Maxime Ripard 
[wens: Add A80 compatible strings to bindings doc; fix pin function
       names based on v1.3 datasheet; constify of_device_id table]
Signed-off-by: Chen-Yu Tsai 
Acked-by: Rob Herring 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Add H3 PIO controller support

2015-12-11T09:15:33+00:00

The H3 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller.

Signed-off-by: Jens Kuske 
Acked-by: Rob Herring 
Acked-by: Maxime Ripard 
Signed-off-by: Linus Walleij

pinctrl: sunxi: add allwinner A83T PIO controller support

2015-10-02T11:09:44+00:00

Allwinner A83T soc port controller has 8 ports.
It has 3 IRQ banks namely PB, PG, PH.
Pinmuxing are different for some pins as compared to
sun8i A23 and A33.

Signed-off-by: Vishnu Patekar 
Acked-by: Maxime Ripard 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Add allwinner A33 PIO controller support

2015-06-04T08:32:11+00:00

A33 PIO has 7 ports which starts from PB and has two interrupt ports.

Signed-off-by: Vishnu Patekar 
Acked-by: Hans de Goede 
Acked-by: Maxime Ripard 
Signed-off-by: Hans de Goede 
Signed-off-by: Linus Walleij

pinctrl: sun6i: Add A31s pinctrl support

2015-01-14T13:21:52+00:00

The A31s is a stripped down version of the A31, as such it is missing some
pins and some functions on some pins.

The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c
with the missing pins and functions removed.

Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
prcm pins are identical between the A31 and the A31s.

Signed-off-by: Hans de Goede 
Acked-by: Maxime Ripard 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Add A80 pinctrl muxing options

2014-10-30T14:56:16+00:00

The A80 has a rather usual pin controller, the only thing out of the ordinary
being that it has 5 interrupts banks, and that some pins have several options
for the same functions.

Signed-off-by: Maxime Ripard 
Signed-off-by: Linus Walleij