linux-toradex.git/drivers/pinctrl/sunxi/pinctrl-sunxi.c, branch v5.2-rc2

pinctrl: sunxi: Support I/O bias voltage setting on H6

2019-04-23T10:31:42+00:00

H6 SoC has a "pio group withstand voltage mode" register (datasheet
description), that needs to be used to select either 1.8V or 3.3V I/O mode,
based on what voltage is powering the respective pin banks and is thus used
for I/O signals.

Add support for configuring this register according to the voltage of the
pin bank regulator (if enabled).

This is similar to the support for I/O bias voltage setting patch for A80
and the same concerns apply. See:

  commit 402bfb3c1352 ("Support I/O bias voltage setting on A80")

Signed-off-by: Ondrej Jirman 
Acked-by: Maxime Ripard 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Prepare for alternative bias voltage setting methods

2019-04-23T10:29:21+00:00

H6 has a different I/O voltage bias setting method than A80. Prepare
existing code for using alternative bias voltage setting methods.

Signed-off-by: Ondrej Jirman 
Acked-by: Maxime Ripard 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Declare set_config on the GPIO chip

2019-04-04T03:54:59+00:00

Our pin controller can configure the pins no matter how they are muxed, so
it makes sense to allow this for GPIOs as well.

Add the generic set_config function so that we can rely on the existing
pinctrl code we have.

Signed-off-by: Maxime Ripard 
Acked-by: Chen-Yu Tsai 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Fix variable assignment syntax

2019-04-04T03:54:55+00:00

Lines are usually ended with a semi-column in C, yet this was copied from a
structure declaration to the init variant while keeping the comma at the
end. Make sure we have a normal syntax, instead of multiple assignments.

Fixes: d83c82ce7ccd ("pinctrl: sunxi: support multiple pin controller")
Signed-off-by: Maxime Ripard 
Acked-by: Chen-Yu Tsai 
Signed-off-by: Linus Walleij

pinctrl: sunxi: implement pin_config_set

2019-04-04T03:54:39+00:00

The sunxi pinctrl only implements the pin_config_group_set callback at the
moment, whereas the gpiochip_generic_config function relies on
pin_config_set. Rework the functions a little to support pin_config_set,
and rely on it for pin_config_group_set.

Signed-off-by: Maxime Ripard 
Acked-by: Chen-Yu Tsai 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Support I/O bias voltage setting on A80

2019-02-11T08:20:58+00:00

The A80 SoC has configuration registers for I/O bias voltage. Incorrect
settings would make the affected peripherals inoperable in some cases,
such as Ethernet RGMII signals biased at 2.5V with the settings still
at 3.3V. However low speed signals such as MDIO on the same group of
pins seem to be unaffected.

Previously there was no way to know what the actual voltage used was,
short of hard-coding a value in the device tree. With the new pin bank
regulator supply support in place, the driver can now query the
regulator for its voltage, and if it's valid (as opposed to being the
dummy regulator), set the bias voltage setting accordingly.

Add a quirk to denote the presence of the configuration registers, and
a function to set the correct setting based on the voltage read back
from the regulator.

This is only done when the regulator is first acquired and enabled.
While it would be nice to have a notifier on the regulator so that when
the voltage changes, the driver can update the setting, in practice no
board currently supports dynamic changing of the I/O voltages.

Signed-off-by: Chen-Yu Tsai 
Acked-by: Maxime Ripard 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Consider pin_base when calculating regulator array index

2019-01-14T15:12:59+00:00

On most newer Allwinner SoCs, there are two pinctrl devices, the PIO and
R_PIO. PIO covers pin-banks PA to PI (PJ and PK have not been seen),
while R_PIO covers PL to PN. The regulator array only has space for 12
entries, which was designed to cover PA to PL. On the A80, the pin banks
go up to PN, which would be the 14th entry in the regulator array.
However since the driver only needs to track regulators for its own pin
banks, the array only needs to have 9 entries, and also take in to
account the value of pin_base, such that the regulator for the first
pin-bank of the pinctrl device, be it "PA" or "PL" uses the first entry
of the array.

Base the regulator array index on pin_base, such that "PA" for PIO and
"PL" for R_PIO both take the first element within their respective
device's regulator array.

Also decrease the size of the regulator array to 9, just enough to cover
"PA" to "PI".

Fixes: 9a2a566adb00 ("pinctrl: sunxi: Deal with per-bank regulators")
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Fix and simplify pin bank regulator handling

2019-01-14T15:09:27+00:00

The new per-pin-bank regulator handling code in the sunxi pinctrl driver
has mismatched conditions for enabling and disabling the regulator: it
is enabled each time a pin is requested, but only disabled when the
pin-bank's reference count reaches zero.

Since we are doing reference counting already, there's no need to enable
the regulator each time a pin is requested. Instead we can just do it
for the first requested pin of each pin-bank. Thus we can reverse the
test and bail out early if it's not the first occurrence.

Fixes: 9a2a566adb00 ("pinctrl: sunxi: Deal with per-bank regulators")
Acked-by: Maxime Ripard 
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Deal with per-bank regulators

2018-12-14T15:07:59+00:00

The Allwinner SoCs have on most of their GPIO banks a regulator input.

This issue was mainly ignored so far because either the regulator was a
static regulator that would be providing power anyway, or the bank was used
for a feature unsupported so far (CSI). For the odd cases, enabling it in
the bootloader was the preferred option.

However, now that we are starting to support those features, and that we
can't really rely on the bootloader for this, we need to model those
regulators as such in the DT.

This is slightly more complicated than what it looks like, since some
regulators will be tied to the PMIC, and in order to have access to the
PMIC bus, you need to mux its pins, which will need the pinctrl driver,
that needs the regulator driver to be registered. And this is how you get a
circular dependency.

In practice however, the hardware cannot fall into this case since it would
result in a completely unusable bus. In order to avoid that circular
dependency, we can thus get and enable the regulators at pin_request time.
We'll then need to account for the references of all the pins of a
particular branch to know when to put the reference, but it works pretty
nicely once implemented.

Signed-off-by: Maxime Ripard 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Fix a memory leak in 'sunxi_pinctrl_build_state()'

2018-10-16T08:03:48+00:00

If 'krealloc()' fails, 'pctl->functions' is set to NULL.
We should instead use a temp variable in order to be able to free the
previously allocated memeory, in case of OOM.

Signed-off-by: Christophe JAILLET 
Acked-by: Maxime Ripard 
Signed-off-by: Linus Walleij