Pull pin control updates from Linus Walleij:
 "Nothing special really, some new drivers, the usual trickle of fixes.

  Oddly not even vary many LLM-assisted fixes, I guess they haven't
  found their way into this subsystem yet.

  Core changes:

   - Support input-debounce-ns pin config property.

  New drivers:

   - Qualcomm:
       - Hawi SoC TLMM and LPASS LPI TLMM
       - Kuno (ARM32!) SoC TLMM
       - MSM8952 SoC TLMM
       - PMAU0102 SPMIO GPIO

   - Starfive JHB100 SoC sys0, sys0h, sys1, sys2, per0, per1,
     per2 per2pok and per3 (apparently strongly modularized silicon)

   - Ambarella CV75

   - Apple T8140 SoC used in iPhone 16 [Pro] and MacBook Neo

   - Econet EN7528

   - Allwinner Sunxi A733

   - Mediatek MT6735

  Improvements:

   - Renesas RZ/3GL: SD channel PoC, I2C power source etc

   - The SCMI pin controller uses generic helpers for handling
     groups and functions"

* tag 'pinctrl-v7.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits)
  pinctrl: stm32: program the EXTI mux from .alloc instead of .activate
  pinctrl: stm32: Fix the unit of the hwspinlock timeout
  pinctrl: stm32: Fix fwnode reference leak in stm32_gpiolib_register_bank()
  dt-bindings: pinctrl: brcm,nsp-gpio: Convert to DT schema
  pinctrl: mediatek: Add MT6735 pinctrl driver
  dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Add bindings for MT6735 pin controller
  dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Document MT6765 pin controller
  dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Add MT6795
  dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Improve pinctrl subnode and property descriptions
  dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Pull pinctrl node changes from MT6795 document
  pinctrl: tegra: xusb: free maps on DT map failure
  pinctrl: sprd: free maps on DT map failure
  pinctrl: kconfig: Select generic pinctrl helpers for scmi pinctrl
  pinctrl: scmi: Replace pinctrl ops get group info with generics
  pinctrl: scmi: Replace pinmux ops get function info with generics
  pinctrl: ambarella: fix NULL vs IS_ERR() bug in amb_pinctrl_register()
  pinctrl: starfive: fix missing CONFIG_OF dependencies
  pinctrl: ambarella: add CONFIG_OF dependency
  pinctrl: apple: Add t8140-pinctrl support
  dt-bindings: pinctrl: apple,pinctrl: Add t8140 compatible
  ...

Pull gpio updates from Bartosz Golaszewski:
 "Nothing stands out as particularly interesting, it's been a calm
  cycle. We have three new drivers, support for more models and lots of
  updates across many modules (details are in the signed tag as usual).
  There are also some minor changes and additions to the in-kernel GPIO
  API.

  GPIO core:
   - provide a new controller API: gpiochip_generic_get_config()
   - return -EOPNOTSUPP instead of -ENODEV to user-space if it requests
     hardware timestamping on systems where it's unavailable (no
     user-space regressions reported)

  New drivers:
   - add a driver for ROHM BD73800 PMIC GPIO controller
   - add a driver for Axiado AX3005 SGPIO controller
   - add a driver for Analog Devices AD7768 GPIO controller

  New hardware support:
   - extend gpio-rcar with support for R-Car X5H (R8A78000)
   - extend gpio-tegra186 with support for Tegra 268

  Driver changes:
   - refactor and improve gpio-rtd1625: switch to modern or better
     fitting interfaces and improve coding style
   - improve error handling of return values of
     platform_get_irq_optional() in several drivers
   - normalize the return value of the gpio_chip::get() callback in
     gpio-siox in order to not propagate invalid values up to the GPIO
     core
   - implement gpio_chip::get_direction() for gpio-pcf857x
   - use managed variants of notifier registration functions in several
     drivers
   - remove legacy gpio_set_value_cansleep() as it has no more users
   - add pinctrl support to gpio-realtek-otto
   - add runtime PM support to the gpio-regmap helper module
   - add more ACPI GPIO quirks for various hardware
   - stop needlessly reading gpio_chip::base in gpio-pxa
   - add support for tracking of direction of generic GPIO chips with no
     direction registers via pinctrl backend to gpio-mmio (use the new
     core API: gpiochip_generic_get_config())
   - use the "safe" variants of debugfs_create_file() in
     gpio-sloppy-analyzer
   - use device name as GPIO chip label in gpio-omap
   - refactor bit ops in gpio-dln2
   - prepare gpio-it87 for upcoming kmalloc_obj() conversion

  Devicetree bindings:
   - document new model in gpio-pca95xx
   - allow the gpio-hogs property in gpio-zynq and fsl,qoriq-gpio
   - allow the gpio-ranges property in gpio-realtek-otto

  Misc fixes:
   - add missing MODULE_ALIAS() to gpio-crystalcove
   - fix a comment typo in example GPIO tools
   - fix unbalanced brackets in documentation
   - add names to regmaps in gpio-mvebu to avoid collisions in debugfs
     output
   - fix GPIO lookup using relative paths in GPIO ACPI"

* tag 'gpio-updates-for-v7.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (63 commits)
  gpiolib: acpi: Fix GPIO lookup using relative path
  gpio: legacy: Kill gpio_set_value_cansleep()
  dt-bindings: gpio: pca95xx: add onnn,pca9655 with nxp,pca9555 fallback
  gpiolib: acpi: Ignore GPIO 11 interrupt on Acer Nitro V 16S AI
  gpio: pxa: stop reading gpio_chip::base in direction callbacks
  gpio: axiado: add AX3005 SGPIO controller support
  dt-bindings: gpio: add Axiado AX3005 SGPIO controller
  gpiolib: acpi: Add quirk for Lenovo IdeaPad Slim 3 15ABR8
  MAINTAINERS: Add ROHM BD73800 PMIC files
  gpio: bd73800: Support ROHM BD73800 PMIC GPIOs
  clk: bd718x7: Support ROHM BD73800
  regulator: bd71828: Support ROHM BD73800
  rtc: bd70528: Support RTC on ROHM BD73800
  mfd: Support for ROHM BD73800 PMIC core
  dt-bindings: mfd: ROHM BD73800 PMIC
  dt-bindings: regulator: ROHM BD73800 regulators
  dt-bindings: rohm,bd*: Ref common ROHM bindings
  dt-bindings: mfd: Common ROHM PMIC properties
  gpio: siox: normalize return value of gpio_get()
  gpio: dln2: use assign_bit() where applicable
  ...

stm32_gpio_domain_activate() writes the EXTI interrupt multiplexer
through a regmap obtained from the generic syscon driver. The irq core
calls .activate from __setup_irq() with the raw desc->lock held, so this
happens in a raw atomic section. regmap-mmio sets fast_io, and syscon
does not ask for a raw spinlock, so the regmap is protected by a
spinlock_t. On PREEMPT_RT that is a sleeping lock, which must not be
taken there. lockdep reports it as soon as a GPIO interrupt is
requested:

 [ BUG: Invalid wait context ]
 7.1.13 #7 Not tainted
 -----------------------------
 kworker/u8:1/29 is trying to lock:
 (syscon:117:(&syscon_config)->lock){....}-{3:3}, at: regmap_lock_spinlock
 other info that might help us debug this:
 context-{5:5}
 5 locks held by kworker/u8:1/29:
  #0: ((wq_completion)async){+.+.}-{0:0}, at: process_one_work
  #1: ((work_completion)(&entry->work)){+.+.}-{0:0}, at: process_one_work
  #2: (&dev->mutex){....}-{4:4}, at: __device_attach_async_helper
  #3: (&desc->request_mutex){+.+.}-{4:4}, at: __setup_irq
  #4: (&irq_desc_lock_class){-...}-{2:2}, at: __setup_irq

The driver was already aware of running in atomic context there: it uses
the _in_atomic() hwspinlock primitives around the very same access. The
syscon lock is the one lock in that section it does not control.

Program the mux from .alloc instead, which runs in a sleepable context.
That callback already owns this resource: it reserves the mux line in
pctl->irqmux_map under irqmux_lock, so writing the value it just claimed
is a natural fit, and the value only depends on the bank.

Nothing requires the mux to be reprogrammed at interrupt startup time:
the domain has no .deactivate, .free() only releases the irqmux_map bit
without touching the registers.

Keep the access inside the existing irqmux_lock section rather than
after it. hwspin_lock_timeout_in_atomic() deliberately skips the local
lock that the other hwspinlock modes take, so its caller is responsible
for disabling preemption and for excluding other local contexts; every
other hwspinlock user in this driver relies on bank->lock for that.
irqmux_lock plays the same role here, and it also turns the mux
reservation and the mux write into a single critical section. Nesting
the regmap spinlock_t inside irqmux_lock, itself a spinlock_t, is what
the wait-context checker expects.

Note that this bounds the semaphore hold time on !PREEMPT_RT only. On
PREEMPT_RT spinlock_t disables neither interrupts nor preemption, so the
hardware semaphore can be held across a preemptible section and a
coprocessor contending for it may poll for an unbounded time. That is
not introduced here: bank->lock is a spinlock_t too, so every existing
hwspinlock user in this driver behaves the same way on PREEMPT_RT.
Removing that exposure requires the EXTI mux regmap to be raw-spinlock
based, which the syscon core does not currently offer, and is left for a
separate change.

While moving the code, release the mux reservation when the hwspinlock
cannot be taken, which the .activate callback had no way of doing.

Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Closes: https://lore.kernel.org/all/20220202174430.pf37tt6lua2op3gc@pengutronix.de/
Signed-off-by: Ju Nan <junan76@163.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>

HWSPNLCK_TIMEOUT is passed to hwspin_lock_timeout_in_atomic(), whose
timeout argument is in milliseconds, not microseconds:

  atomic_delay += HWSPINLOCK_RETRY_DELAY_US;
  if (atomic_delay > to * 1000)
          return -ETIMEDOUT;

The hwspinlock core documents this explicitly:

  If the mode is HWLOCK_IN_ATOMIC (called from an atomic context) the
  timeout is handled with busy-waiting delays, hence shall not exceed
  few msecs.

Fixes: 290a9f937e5a ("pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() API")
Signed-off-by: Ju Nan <junan76@163.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>

intel-pinctrl for v7.4-1

* Enable pure platform device enumeration for the Intel pin control

Signed-off-by: Linus Walleij <linusw@kernel.org>

stm32_gpiolib_register_bank() walks the "gpio-ranges" property with
fwnode_property_get_reference_args().  As documented in
drivers/base/property.c:

 * The caller is responsible for calling fwnode_handle_put() on the
 * returned @args->fwnode pointer.

The returned reference is never put.  The function calls the helper
twice, once directly and then repeatedly in a while loop, and each
call overwrites args, so only the last reference is even reachable
and all the earlier ones are leaked for good.

Put the reference as soon as args.args[] has been consumed, both for
the initial call and for every iteration of the loop.

Found by code review.

Cc: stable@vger.kernel.org
Fixes: bb949ed9b16b ("pinctrl: stm32: Switch to use for_each_gpiochip_node() helper")
Signed-off-by: Ma Ke <make_ruc2021@163.com>
Reviewed-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>

init_pins_table() adds to npins in the driver's static descriptor, so
after a probe deferral the count doubles and the next probe fails with
"pin 0 already registered". Reset it first.

Signed-off-by: Pablo Mazzini <pmazzini@gmail.com>
Fixes: f5e2cd34b12f ("pinctrl: sunxi: allow reading mux values from DT")
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>

Qualcomm pin control updates for v7.4-rc1

New drivers:
- add the TLMM drivers for Kuno and MSM8952
- add the LPASS LPI driver for Hawi

New model support:
- support PMAU0102 GPIO in pinctrl-spmi-gpio

Driver improvements:
- fix/unify naming convention in defines specific to Qualcomm pinctrl
  drivers
- extend debugfs verbosity for pinctrl-lpass-lpi
- make the return type from kcalloc() const in tlmm-test

Devicetree bindings:
- add binding documents for new drivers
- document compatibles for new models
- document the gpio-line-names property for qcom,sc8280xp-tlmm

Signed-off-by: Linus Walleij <linusw@kernel.org>

Qualcomm pin control fixes for v7.3-rc7

- fix intr_target_width in several qualcomm pinctrl drivers
- make direction changes exclusive in pinctrl-spmi-gpio
- fix function issues in pinctrl-ipq5018
- add missing OF module alias to pinctrl-ipq5210
- split QUP1 SE2/SE3 into lane-pair functions

Signed-off-by: Linus Walleij <linusw@kernel.org>

Add a driver for the MediaTek MT6735 SoC pin controller. This driver
also supports the pin controller on MT6735M, which lacks 6 physical
pins (198-203) used for MSDC2 on MT6735.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>