linux-toradex.git/drivers/pinctrl, branch v4.16

pinctrl: samsung: Validate alias coming from DT

2018-03-08T12:02:26+00:00

Driver uses alias from Device Tree as an index of pin controller data
array.  In case of a wrong DTB or an out-of-tree DTB, the alias could be
outside of this data array leading to out-of-bounds access.

Depending on binary and memory layout, this could be handled properly
(showing error like "samsung-pinctrl 3860000.pinctrl: driver data not
available") or could lead to exceptions.

Reported-by: Geert Uytterhoeven 
Cc: 
Fixes: 30574f0db1b1 ("pinctrl: add samsung pinctrl and gpiolib driver")
Signed-off-by: Krzysztof Kozlowski 
Reviewed-by: Geert Uytterhoeven 
Acked-by: Tomasz Figa 
Signed-off-by: Linus Walleij

pinctrl: sh-pfc: r8a7795: remove duplicate of CLKOUT pin in pinmux_pins[]

2018-03-08T12:02:01+00:00

When adding GP-1-28 port pin support it was forgotten to remove the
CLKOUT pin from the list of pins that are not associated with a GPIO
port in pinmux_pins[]. This results in a warning when reading the
pinctrl files in sysfs as the CLKOUT pin is still added as a none GPIO
pin. Fix this by removing the duplicated entry which is no longer
needed.

~ # cat /sys/kernel/debug/pinctrl/e6060000.pin-controller/pinconf-pins
[   89.432081] ------------[ cut here ]------------
[   89.436904] Pin 496 is not in bias info list
[   89.441252] WARNING: CPU: 1 PID: 456 at drivers/pinctrl/sh-pfc/core.c:408 sh_pfc_pin_to_bias_reg+0xb0/0xb8
[   89.451002] CPU: 1 PID: 456 Comm: cat Not tainted 4.16.0-rc1-arm64-renesas-00048-gdfafc344a4f24dde #12
[   89.460394] Hardware name: Renesas Salvator-X 2nd version board based on r8a7795 ES2.0+ (DT)
[   89.468910] pstate: 80000085 (Nzcv daIf -PAN -UAO)
[   89.473747] pc : sh_pfc_pin_to_bias_reg+0xb0/0xb8
[   89.478495] lr : sh_pfc_pin_to_bias_reg+0xb0/0xb8
[   89.483241] sp : ffff00000aff3ab0
[   89.486587] x29: ffff00000aff3ab0 x28: ffff00000893c698
[   89.491955] x27: ffff000008ad7d98 x26: 0000000000000000
[   89.497323] x25: ffff8006fb3f5028 x24: ffff8006fb3f5018
[   89.502690] x23: 0000000000000001 x22: 00000000000001f0
[   89.508057] x21: ffff8006fb3f5018 x20: ffff000008bef000
[   89.513423] x19: 0000000000000000 x18: ffffffffffffffff
[   89.518790] x17: 0000000000006c4a x16: ffff000008d67c98
[   89.524157] x15: 0000000000000001 x14: ffff00000896ca98
[   89.529524] x13: 00000000cce5f611 x12: ffff8006f8d3b5a8
[   89.534891] x11: ffff00000981e000 x10: ffff000008befa08
[   89.540258] x9 : ffff8006f9b987a0 x8 : ffff000008befa08
[   89.545625] x7 : ffff000008137094 x6 : 0000000000000000
[   89.550991] x5 : 0000000000000000 x4 : 0000000000000001
[   89.556357] x3 : 0000000000000007 x2 : 0000000000000007
[   89.561723] x1 : 1ff24f80f1818600 x0 : 0000000000000000
[   89.567091] Call trace:
[   89.569561]  sh_pfc_pin_to_bias_reg+0xb0/0xb8
[   89.573960]  r8a7795_pinmux_get_bias+0x30/0xc0
[   89.578445]  sh_pfc_pinconf_get+0x1e0/0x2d8
[   89.582669]  pin_config_get_for_pin+0x20/0x30
[   89.587067]  pinconf_generic_dump_one+0x180/0x1c8
[   89.591815]  pinconf_generic_dump_pins+0x84/0xd8
[   89.596476]  pinconf_pins_show+0xc8/0x130
[   89.600528]  seq_read+0xe4/0x510
[   89.603789]  full_proxy_read+0x60/0x90
[   89.607576]  __vfs_read+0x30/0x140
[   89.611010]  vfs_read+0x90/0x170
[   89.614269]  SyS_read+0x60/0xd8
[   89.617443]  __sys_trace_return+0x0/0x4
[   89.621314] ---[ end trace 99c8d0d39c13e794 ]---

Fixes: 82d2de5a4f646f72 ("pinctrl: sh-pfc: r8a7795: Add GP-1-28 port pin support")
Reviewed-and-tested-by: Geert Uytterhoeven 
Signed-off-by: Niklas Söderlund 
Signed-off-by: Linus Walleij

pinctrl: meson-axg: adjust uart_ao_b pin group naming

2018-02-12T09:47:36+00:00

Simply adjust the pin group to _x _y _z style, as to
keep the consistency in DT with previous naming scheme.

Fixes: 83c566806a68 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC")
Signed-off-by: Yixun Lan 
Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2018-02-02T22:22:53+00:00

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.16 kernel cycle.
  Like with GPIO it is actually a bit calm this time.

  Core changes:

   - After lengthy discussions and partly due to my ignorance, we have
     merged a patch making pinctrl_force_default() and
     pinctrl_force_sleep() reprogram the states into the hardware of any
     hogged pins, even if they are already in the desired state.

     This only apply to hogged pins since groups of pins owned by
     drivers need to be managed by each driver, lest they could not do
     things like runtime PM and put pins to sleeping state even if the
     system as a whole is not in sleep.

  New drivers:

   - New driver for the Microsemi Ocelot SoC. This is used in ethernet
     switches.

   - The X-Powers AXP209 GPIO driver was extended to also deal with pin
     control and moved over from the GPIO subsystem. This circuit is a
     mixed-mode integrated circuit which is part of AllWinner designs.

   - New subdriver for the Qualcomm MSM8998 SoC, core of a high end
     mobile devices (phones) chipset.

   - New subdriver for the ST Microelectronics STM32MP157 MPU and
     STM32F769 MCU from the STM32 family.

   - New subdriver for the MediaTek MT7622 SoC. This is used for
     routers, repeater, gateways and such network infrastructure.

   - New subdriver for the NXP (former Freescale) i.MX 6ULL. This SoC
     has multimedia features and target "smart devices", I guess in-car
     entertainment, in-flight entertainment, industrial control panels
     etc.

  General improvements:

   - Incremental improvements on the SH-PFC subdrivers for things like
     the CAN bus.

   - Enable the glitch filter on Baytrail GPIOs used for interrupts.

   - Proper handling of pins to GPIO ranges on the Semtec SX150X

   - An IRQ setup ordering fix on MCP23S08.

   - A good set of janitorial coding style fixes"

* tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (102 commits)
  pinctrl: mcp23s08: fix irq setup order
  pinctrl: Forward declare struct device
  pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding
  pinctrl: stm32: add STM32F769 MCU support
  pinctrl: sx150x: Add a static gpio/pinctrl pin range mapping
  pinctrl: sx150x: Register pinctrl before adding the gpiochip
  pinctrl: sx150x: Unregister the pinctrl on release
  pinctrl: ingenic: Remove redundant dev_err call in ingenic_pinctrl_probe()
  pinctrl: sprd: Use seq_putc() in sprd_pinconf_group_dbg_show()
  pinctrl: pinmux: Use seq_putc() in pinmux_pins_show()
  pinctrl: abx500: Use seq_putc() in abx500_gpio_dbg_show()
  pinctrl: mediatek: mt7622: align error handling of mtk_hw_get_value call
  pinctrl: mediatek: mt7622: fix potential uninitialized value being returned
  pinctrl: uniphier: refactor drive strength get/set functions
  pinctrl: imx7ulp: constify struct imx_cfg_params_decode
  pinctrl: imx: constify struct imx_pinctrl_soc_info
  pinctrl: imx7d: simplify imx7d_pinctrl_probe
  pinctrl: imx: use struct imx_pinctrl_soc_info as a const
  pinctrl: sunxi-pinctrl: fix pin funtion can not be match correctly.
  pinctrl: qcom: Add msm8998 pinctrl driver
  ...

Merge tag 'gpio-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

2018-01-31T20:25:27+00:00

Pull GPIO updates from Linus Walleij:
"The is the bulk of GPIO changes for the v4.16 kernel cycle. It is
pretty calm this time around I think. I even got time to get to things
like starting to clean up header includes.

Core changes:

- Disallow open drain and open source flags to be set simultaneously.
This doesn't make electrical sense, and would the hardware actually
respond to this setting, the result would be short circuit.

- ACPI GPIO has a new core infrastructure for handling quirks. The
quirks are there to deal with broken ACPI tables centrally instead
of pushing the work to individual drivers. In the world of BIOS
writers, the ACPI tables are perfect. Until they find a mistake in
it. When such a mistake is found, we can patch it with a quirk. It
should never happen, the problem is that it happens. So we
accomodate for it.

- Several documentation updates.

- Revert the patch setting up initial direction state from reading
the device. This was causing bad things for drivers that can't read
status on all its pins. It is only affecting debugfs information
quality.

- Label descriptors with the device name if no explicit label is
passed in.

- Pave the ground for transitioning SPI and regulators to use GPIO
descriptors by implementing some quirks in the device tree GPIO
parsing code.

New drivers:

- New driver for the Access PCIe IDIO 24 family.

Other:

- Major refactorings and improvements to the GPIO mockup driver used
for test and verification.

- Moved the AXP209 driver over to pin control since it gained a pin
control back-end. These patches will appear (with the same hashes)
in the pin control pull request as well.

- Convert the onewire GPIO driver w1-gpio to use descriptors. This is
merged here since the W1 maintainers send very few pull requests
and he ACKed it.

- Start to clean up driver headers using to just use
as appropriate"

* tag 'gpio-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (103 commits)
gpio: Timestamp events in hardirq handler
gpio: Fix kernel stack leak to userspace
gpio: Fix a documentation spelling mistake
gpio: Documentation update
gpiolib: remove redundant initialization of pointer desc
gpio: of: Fix NPE from OF flags
gpio: stmpe: Delete an unnecessary variable initialisation in stmpe_gpio_probe()
gpio: stmpe: Move an assignment in stmpe_gpio_probe()
gpio: stmpe: Improve a size determination in stmpe_gpio_probe()
gpio: stmpe: Use seq_putc() in stmpe_dbg_show()
gpio: No NULL owner
gpio: stmpe: i2c transfer are forbiden in atomic context
gpio: davinci: Include proper header
gpio: da905x: Include proper header
gpio: cs5535: Include proper header
gpio: crystalcove: Include proper header
gpio: bt8xx: Include proper header
gpio: bcm-kona: Include proper header
gpio: arizona: Include proper header
gpio: amd8111: Include proper header
...

pinctrl: mcp23s08: fix irq setup order

2018-01-30T14:17:14+00:00

When using mcp23s08 module with gpio-keys, often (50% of boots)
it fails to get irq numbers with message:
"gpio-keys keys: Unable to get irq number for GPIO 0, error -6".
Seems that irqs must be setup before devm_gpiochip_add_data().

Cc: stable@vger.kernel.org
Signed-off-by: Dmitry Mastykin 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding

2018-01-22T08:55:05+00:00

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Linus Walleij

pinctrl: stm32: add STM32F769 MCU support

2018-01-22T08:28:08+00:00

This patch which adds STM32F769 pinctrl and GPIO support, relies on the
generic STM32 pinctrl driver.

Signed-off-by: Alexandre Torgue 
Acked-by: Patrice CHOTARD 
Signed-off-by: Linus Walleij

pinctrl: sx150x: Add a static gpio/pinctrl pin range mapping

2018-01-18T10:04:47+00:00

Without such a range, gpiolib fails with -EPROBE_DEFER, pending the
addition of the range. So, without a range, gpiolib will keep
deferring indefinitely.

Cc: stable@vger.kernel.org
Fixes: 9e80f9064e73 ("pinctrl: Add SX150X GPIO Extender Pinctrl Driver")
Fixes: e10f72bf4b3e ("gpio: gpiolib: Generalise state persistence beyond sleep")
Suggested-by: Linus Walleij 
Signed-off-by: Peter Rosin 
Signed-off-by: Linus Walleij

pinctrl: sx150x: Register pinctrl before adding the gpiochip

2018-01-18T10:04:43+00:00

Various gpiolib activity depend on the pinctrl to be up and kicking.
Therefore, register the pinctrl before adding a gpiochip.

Cc: stable@vger.kernel.org
Suggested-by: Linus Walleij 
Signed-off-by: Peter Rosin 
Signed-off-by: Linus Walleij