linux-toradex.git/drivers/pinctrl, branch v4.6-rc6

pinctrl: single: Fix pcs_parse_bits_in_pinctrl_entry to use __ffs than ffs

2016-04-15T09:26:55+00:00

pcs_parse_bits_in_pinctrl_entry uses ffs which gives bit indices
ranging from 1 to MAX. This leads to a corner case where we try to request
the pin number = MAX and fails.

bit_pos value is being calculted using ffs. pin_num_from_lsb uses
bit_pos value. pins array is populated with:

pin + pin_num_from_lsb.

The above is 1 more than usual bit indices as bit_pos uses ffs to compute
first set bit. Hence the last of the pins array is populated with the MAX
value and not MAX - 1 which causes error when we call pin_request.

mask_pos is rightly calculated as ((pcs->fmask) << (bit_pos - 1))
Consequently val_pos and submask are correct.

Hence use __ffs which gives (ffs(x) - 1) as the first bit set.

fixes: 4e7e8017a8 ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules")
Signed-off-by: Keerthy 
Acked-by: Tony Lindgren 
Signed-off-by: Linus Walleij

pinctrl: mediatek: correct debounce time unit in mtk_gpio_set_debounce

2016-04-15T08:28:04+00:00

The debounce time unit for gpio_chip.set_debounce is us but
mtk_gpio_set_debounce regard it as ms.
Fix this by correct debounce time array dbnc_arr so it can find correct
debounce setting. Debounce time for first debounce setting is 500us,
correct this as well.

While I'm at it, also change the debounce time array name to
"debounce_time" for readability.

Cc: stable@vger.kernel.org
Signed-off-by: Yingjoe Chen 
Reviewed-by: Daniel Kurtz 
Acked-by: Hongzhou Yang 
Signed-off-by: Linus Walleij

pinctrl: imx: Kconfig: PINCTRL_IMX select REGMAP

2016-04-14T12:19:00+00:00

Regmap functionality has been integrated into pinctrl-imx.c with commit
8626ada8 which might trigger build failures when regmap is not selected
otherwise. Hence, make Kconfig aware about this new dependency.

Signed-off-by: Alexander Kurz 
Acked-by: Philipp Zabel 
Acked-by: Shawn Guo 
Signed-off-by: Linus Walleij

Revert "Revert "pinctrl: lantiq: Implement gpio_chip.to_irq""

2016-04-01T13:21:27+00:00

This reverts commit 446f59acb70b70a425ea4105277a71eb615327cd.

pinctrl: qcom: ipq4019: fix register offsets

2016-03-31T09:56:13+00:00

For this SoC the register offsets changed from previous versions to be
separated by a larger amount.

Signed-off-by: Matthew McClintock 
Acked-by: Björn Andersson 
Signed-off-by: Linus Walleij

pinctrl: qcom: ipq4019: fix the function enum for gpio mode

2016-03-31T09:55:57+00:00

Without this, we would fail to set the mode to gpio if trying to
configure for that mode

Signed-off-by: Matthew McClintock 
Acked-by: Björn Andersson 
Signed-off-by: Linus Walleij

pinctrl: qcom: ipq4019: set ngpios to correct value

2016-03-31T09:53:02+00:00

This should have been bumped to 100 when the extra pins
were added in the original pinctrl patch

Signed-off-by: Matthew McClintock 
Acked-by: Björn Andersson 
Signed-off-by: Linus Walleij

pinctrl: nomadik: fix pull debug print inversion

2016-03-31T08:45:26+00:00

Pull up was reported as pull down and vice versa. Fix this.

Fixes: 8f1774a2a971 "pinctrl: nomadik: improve GPIO debug prints"
Signed-off-by: Linus Walleij

pinctrl: intel: implement gpio_irq_enable

2016-03-30T08:57:52+00:00

There is unexpected gpio interrupt after irq_enable. If not
implemeted gpio_irq_enable callback, irq_enable calls irq_unmask
instead. But if there was interrupt set before the irq_enable,
unmask it may trigger the unexpected interrupt. By implementing
the gpio_irq_enable callback, do interrupt status ack, the issue
has gone.

Signed-off-by: Qi Zheng 
Signed-off-by: Mika Westerberg 
Signed-off-by: Qipeng Zha 
Signed-off-by: Linus Walleij

pinctrl: intel: make the high level interrupt working

2016-03-30T08:57:52+00:00

High level trigger mode of GPIO interrupt is not set correctly
in intel_gpio_irq_type(), and will make this kind of interrupt
not respond.

Signed-off-by: Qi Zheng 
Signed-off-by: Qipeng Zha 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij