<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/drivers/powercap/intel_rapl_msr.c, branch v7.0-rc2</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>powercap: intel_rapl: Remove incorrect CPU check in PMU context</title>
<updated>2026-02-11T20:03:39+00:00</updated>
<author>
<name>Kuppuswamy Sathyanarayanan</name>
<email>sathyanarayanan.kuppuswamy@linux.intel.com</email>
</author>
<published>2026-02-09T23:43:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=7537bae8b6eb635583e0e6260f61d13ddbd52087'/>
<id>7537bae8b6eb635583e0e6260f61d13ddbd52087</id>
<content type='text'>
The RAPL MSR read path incorrectly validates CPU context when called
from the PMU subsystem:

    if (atomic) {
        if (unlikely(smp_processor_id() != cpu))
            return -EIO;
        rdmsrq(ra-&gt;reg.msr, ra-&gt;value);
    }

This check fails for package-scoped MSRs like RAPL energy counters,
which are readable from any CPU within the package.

The perf tool avoids hitting this check by validating against
/sys/bus/event_source/devices/power/cpumask before opening events.
However, turbostat does not perform this validation and may attempt
reads from non-lead CPUs, causing the check to fail and return zero
power values.

Since package-scoped MSRs are architecturally accessible from any CPU
in the package, remove the CPU matching check.

Also rename 'atomic' to 'pmu_ctx' to clarify this indicates PMU context
where rdmsrq() can be used directly instead of rdmsrl_safe_on_cpu().

Fixes: 748d6ba43afd ("powercap: intel_rapl: Enable MSR-based RAPL PMU support")
Signed-off-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
Tested-by: Furquim Ulisses &lt;ulisses.furquim@intel.com&gt;
Reviewed-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Link: https://patch.msgid.link/20260209234310.1440722-2-sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The RAPL MSR read path incorrectly validates CPU context when called
from the PMU subsystem:

    if (atomic) {
        if (unlikely(smp_processor_id() != cpu))
            return -EIO;
        rdmsrq(ra-&gt;reg.msr, ra-&gt;value);
    }

This check fails for package-scoped MSRs like RAPL energy counters,
which are readable from any CPU within the package.

The perf tool avoids hitting this check by validating against
/sys/bus/event_source/devices/power/cpumask before opening events.
However, turbostat does not perform this validation and may attempt
reads from non-lead CPUs, causing the check to fail and return zero
power values.

Since package-scoped MSRs are architecturally accessible from any CPU
in the package, remove the CPU matching check.

Also rename 'atomic' to 'pmu_ctx' to clarify this indicates PMU context
where rdmsrq() can be used directly instead of rdmsrl_safe_on_cpu().

Fixes: 748d6ba43afd ("powercap: intel_rapl: Enable MSR-based RAPL PMU support")
Signed-off-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
Tested-by: Furquim Ulisses &lt;ulisses.furquim@intel.com&gt;
Reviewed-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Link: https://patch.msgid.link/20260209234310.1440722-2-sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powercap: intel_rapl: Add PL4 support for Ice Lake</title>
<updated>2026-01-15T20:14:54+00:00</updated>
<author>
<name>Daniel Tang</name>
<email>danielzgtg.opensource@gmail.com</email>
</author>
<published>2026-01-15T02:01:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=54b3cd55a515c7c0fcfa0c1f0b10d62c11d64bcc'/>
<id>54b3cd55a515c7c0fcfa0c1f0b10d62c11d64bcc</id>
<content type='text'>
Microsoft Surface Pro 7 firmware throttles the processor upon
boot/resume. Userspace needs to be able to restore the correct value.

Link: https://github.com/linux-surface/linux-surface/issues/706
Signed-off-by: Daniel Tang &lt;danielzgtg.opensource@gmail.com&gt;
Link: https://patch.msgid.link/6088605.ChMirdbgyp@daniel-desktop3
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Microsoft Surface Pro 7 firmware throttles the processor upon
boot/resume. Userspace needs to be able to restore the correct value.

Link: https://github.com/linux-surface/linux-surface/issues/706
Signed-off-by: Daniel Tang &lt;danielzgtg.opensource@gmail.com&gt;
Link: https://patch.msgid.link/6088605.ChMirdbgyp@daniel-desktop3
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powercap: intel_rapl: Fix possible recursive lock warning</title>
<updated>2025-12-17T16:24:28+00:00</updated>
<author>
<name>Srinivas Pandruvada</name>
<email>srinivas.pandruvada@linux.intel.com</email>
</author>
<published>2025-12-17T15:34:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=dcd0b625fe440d68bb4b97c71d18ca48ecd6e594'/>
<id>dcd0b625fe440d68bb4b97c71d18ca48ecd6e594</id>
<content type='text'>
With the RAPL PMU addition, there is a recursive locking when CPU online
callback function calls rapl_package_add_pmu(). Here cpu_hotplug_lock
is already acquired by cpuhp_thread_fun() and rapl_package_add_pmu()
tries to acquire again.

&lt;4&gt;[ 8.197433] ============================================
&lt;4&gt;[ 8.197437] WARNING: possible recursive locking detected
&lt;4&gt;[ 8.197440] 6.19.0-rc1-lgci-xe-xe-4242-05b7c58b3367dca84+ #1 Not tainted
&lt;4&gt;[ 8.197444] --------------------------------------------
&lt;4&gt;[ 8.197447] cpuhp/0/20 is trying to acquire lock:
&lt;4&gt;[ 8.197450] ffffffff83487870 (cpu_hotplug_lock){++++}-{0:0}, at:
rapl_package_add_pmu+0x37/0x370 [intel_rapl_common]
&lt;4&gt;[ 8.197463]
but task is already holding lock:
&lt;4&gt;[ 8.197466] ffffffff83487870 (cpu_hotplug_lock){++++}-{0:0}, at:
cpuhp_thread_fun+0x6d/0x290
&lt;4&gt;[ 8.197477]
other info that might help us debug this:
&lt;4&gt;[ 8.197480] Possible unsafe locking scenario:

&lt;4&gt;[ 8.197483] CPU0
&lt;4&gt;[ 8.197485] ----
&lt;4&gt;[ 8.197487] lock(cpu_hotplug_lock);
&lt;4&gt;[ 8.197490] lock(cpu_hotplug_lock);
&lt;4&gt;[ 8.197493]
*** DEADLOCK ***
..
..
&lt;4&gt;[ 8.197542] __lock_acquire+0x146e/0x2790
&lt;4&gt;[ 8.197548] lock_acquire+0xc4/0x2c0
&lt;4&gt;[ 8.197550] ? rapl_package_add_pmu+0x37/0x370 [intel_rapl_common]
&lt;4&gt;[ 8.197556] cpus_read_lock+0x41/0x110
&lt;4&gt;[ 8.197558] ? rapl_package_add_pmu+0x37/0x370 [intel_rapl_common]
&lt;4&gt;[ 8.197561] rapl_package_add_pmu+0x37/0x370 [intel_rapl_common]
&lt;4&gt;[ 8.197565] rapl_cpu_online+0x85/0x87 [intel_rapl_msr]
&lt;4&gt;[ 8.197568] ? __pfx_rapl_cpu_online+0x10/0x10 [intel_rapl_msr]
&lt;4&gt;[ 8.197570] cpuhp_invoke_callback+0x41f/0x6c0
&lt;4&gt;[ 8.197573] ? cpuhp_thread_fun+0x6d/0x290
&lt;4&gt;[ 8.197575] cpuhp_thread_fun+0x1e2/0x290
&lt;4&gt;[ 8.197578] ? smpboot_thread_fn+0x26/0x290
&lt;4&gt;[ 8.197581] smpboot_thread_fn+0x12f/0x290
&lt;4&gt;[ 8.197584] ? __pfx_smpboot_thread_fn+0x10/0x10
&lt;4&gt;[ 8.197586] kthread+0x11f/0x250
&lt;4&gt;[ 8.197589] ? __pfx_kthread+0x10/0x10
&lt;4&gt;[ 8.197592] ret_from_fork+0x344/0x3a0
&lt;4&gt;[ 8.197595] ? __pfx_kthread+0x10/0x10
&lt;4&gt;[ 8.197597] ret_from_fork_asm+0x1a/0x30
&lt;4&gt;[ 8.197604] &lt;/TASK&gt;

Fix this issue in the same way as rapl powercap package domain is added
from the same CPU online callback by introducing another interface which
doesn't call cpus_read_lock(). Add rapl_package_add_pmu_locked() and
rapl_package_remove_pmu_locked() which don't call cpus_read_lock().

Fixes: 748d6ba43afd ("powercap: intel_rapl: Enable MSR-based RAPL PMU support")
Reported-by: Borah, Chaitanya Kumar &lt;chaitanya.kumar.borah@intel.com&gt;
Closes: https://lore.kernel.org/linux-pm/5427ede1-57a0-43d1-99f3-8ca4b0643e82@intel.com/T/#u
Tested-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
Tested-by: RavitejaX Veesam &lt;ravitejax.veesam@intel.com&gt;
Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Link: https://patch.msgid.link/20251217153455.3560176-1-srinivas.pandruvada@linux.intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
With the RAPL PMU addition, there is a recursive locking when CPU online
callback function calls rapl_package_add_pmu(). Here cpu_hotplug_lock
is already acquired by cpuhp_thread_fun() and rapl_package_add_pmu()
tries to acquire again.

&lt;4&gt;[ 8.197433] ============================================
&lt;4&gt;[ 8.197437] WARNING: possible recursive locking detected
&lt;4&gt;[ 8.197440] 6.19.0-rc1-lgci-xe-xe-4242-05b7c58b3367dca84+ #1 Not tainted
&lt;4&gt;[ 8.197444] --------------------------------------------
&lt;4&gt;[ 8.197447] cpuhp/0/20 is trying to acquire lock:
&lt;4&gt;[ 8.197450] ffffffff83487870 (cpu_hotplug_lock){++++}-{0:0}, at:
rapl_package_add_pmu+0x37/0x370 [intel_rapl_common]
&lt;4&gt;[ 8.197463]
but task is already holding lock:
&lt;4&gt;[ 8.197466] ffffffff83487870 (cpu_hotplug_lock){++++}-{0:0}, at:
cpuhp_thread_fun+0x6d/0x290
&lt;4&gt;[ 8.197477]
other info that might help us debug this:
&lt;4&gt;[ 8.197480] Possible unsafe locking scenario:

&lt;4&gt;[ 8.197483] CPU0
&lt;4&gt;[ 8.197485] ----
&lt;4&gt;[ 8.197487] lock(cpu_hotplug_lock);
&lt;4&gt;[ 8.197490] lock(cpu_hotplug_lock);
&lt;4&gt;[ 8.197493]
*** DEADLOCK ***
..
..
&lt;4&gt;[ 8.197542] __lock_acquire+0x146e/0x2790
&lt;4&gt;[ 8.197548] lock_acquire+0xc4/0x2c0
&lt;4&gt;[ 8.197550] ? rapl_package_add_pmu+0x37/0x370 [intel_rapl_common]
&lt;4&gt;[ 8.197556] cpus_read_lock+0x41/0x110
&lt;4&gt;[ 8.197558] ? rapl_package_add_pmu+0x37/0x370 [intel_rapl_common]
&lt;4&gt;[ 8.197561] rapl_package_add_pmu+0x37/0x370 [intel_rapl_common]
&lt;4&gt;[ 8.197565] rapl_cpu_online+0x85/0x87 [intel_rapl_msr]
&lt;4&gt;[ 8.197568] ? __pfx_rapl_cpu_online+0x10/0x10 [intel_rapl_msr]
&lt;4&gt;[ 8.197570] cpuhp_invoke_callback+0x41f/0x6c0
&lt;4&gt;[ 8.197573] ? cpuhp_thread_fun+0x6d/0x290
&lt;4&gt;[ 8.197575] cpuhp_thread_fun+0x1e2/0x290
&lt;4&gt;[ 8.197578] ? smpboot_thread_fn+0x26/0x290
&lt;4&gt;[ 8.197581] smpboot_thread_fn+0x12f/0x290
&lt;4&gt;[ 8.197584] ? __pfx_smpboot_thread_fn+0x10/0x10
&lt;4&gt;[ 8.197586] kthread+0x11f/0x250
&lt;4&gt;[ 8.197589] ? __pfx_kthread+0x10/0x10
&lt;4&gt;[ 8.197592] ret_from_fork+0x344/0x3a0
&lt;4&gt;[ 8.197595] ? __pfx_kthread+0x10/0x10
&lt;4&gt;[ 8.197597] ret_from_fork_asm+0x1a/0x30
&lt;4&gt;[ 8.197604] &lt;/TASK&gt;

Fix this issue in the same way as rapl powercap package domain is added
from the same CPU online callback by introducing another interface which
doesn't call cpus_read_lock(). Add rapl_package_add_pmu_locked() and
rapl_package_remove_pmu_locked() which don't call cpus_read_lock().

Fixes: 748d6ba43afd ("powercap: intel_rapl: Enable MSR-based RAPL PMU support")
Reported-by: Borah, Chaitanya Kumar &lt;chaitanya.kumar.borah@intel.com&gt;
Closes: https://lore.kernel.org/linux-pm/5427ede1-57a0-43d1-99f3-8ca4b0643e82@intel.com/T/#u
Tested-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
Tested-by: RavitejaX Veesam &lt;ravitejax.veesam@intel.com&gt;
Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Link: https://patch.msgid.link/20251217153455.3560176-1-srinivas.pandruvada@linux.intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powercap: intel_rapl: Enable MSR-based RAPL PMU support</title>
<updated>2025-11-21T20:47:08+00:00</updated>
<author>
<name>Kuppuswamy Sathyanarayanan</name>
<email>sathyanarayanan.kuppuswamy@linux.intel.com</email>
</author>
<published>2025-11-21T00:05:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=748d6ba43afde7e9ac27443233203995cc15d235'/>
<id>748d6ba43afde7e9ac27443233203995cc15d235</id>
<content type='text'>
Currently, RAPL PMU support requires adding CPU model entries to
arch/x86/events/rapl.c for each new generation. However, RAPL MSRs are
not architectural and require platform-specific customization, making
arch/x86 an inappropriate location for this functionality.

The powercap subsystem already handles RAPL functionality and is the
natural place to consolidate all RAPL features. The powercap RAPL
driver already includes PMU support for TPMI-based RAPL interfaces,
making it straightforward to extend this support to MSR-based RAPL
interfaces as well.

This consolidation eliminates the need to maintain RAPL support in
multiple subsystems and provides a unified approach for both TPMI and
MSR-based RAPL implementations.

The MSR-based PMU support includes the following updates:

 1. Register MSR-based PMU support for the supported platforms
    and unregister it when no online CPUs remain in the package.

 2. Remove existing checks that restrict RAPL PMU support to TPMI-based
    interfaces and extend the logic to allow MSR-based RAPL interfaces.

 3. Define a CPU model list to determine which processors should
    register RAPL PMU interface through the powercap driver for
    MSR-based RAPL, excluding those that support TPMI interface.
    This list prevents conflicts with existing arch/x86 PMU code
    that already registers RAPL PMU for some processors. Add
    Panther Lake &amp; Wildcat Lake to the CPU models list.

Signed-off-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
Reviewed-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
[ rjw: Changelog edits ]
Link: https://patch.msgid.link/20251121000539.386069-3-sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Currently, RAPL PMU support requires adding CPU model entries to
arch/x86/events/rapl.c for each new generation. However, RAPL MSRs are
not architectural and require platform-specific customization, making
arch/x86 an inappropriate location for this functionality.

The powercap subsystem already handles RAPL functionality and is the
natural place to consolidate all RAPL features. The powercap RAPL
driver already includes PMU support for TPMI-based RAPL interfaces,
making it straightforward to extend this support to MSR-based RAPL
interfaces as well.

This consolidation eliminates the need to maintain RAPL support in
multiple subsystems and provides a unified approach for both TPMI and
MSR-based RAPL implementations.

The MSR-based PMU support includes the following updates:

 1. Register MSR-based PMU support for the supported platforms
    and unregister it when no online CPUs remain in the package.

 2. Remove existing checks that restrict RAPL PMU support to TPMI-based
    interfaces and extend the logic to allow MSR-based RAPL interfaces.

 3. Define a CPU model list to determine which processors should
    register RAPL PMU interface through the powercap driver for
    MSR-based RAPL, excluding those that support TPMI interface.
    This list prevents conflicts with existing arch/x86 PMU code
    that already registers RAPL PMU for some processors. Add
    Panther Lake &amp; Wildcat Lake to the CPU models list.

Signed-off-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
Reviewed-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
[ rjw: Changelog edits ]
Link: https://patch.msgid.link/20251121000539.386069-3-sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powercap: intel_rapl: Prepare read_raw() interface for atomic-context callers</title>
<updated>2025-11-21T20:47:08+00:00</updated>
<author>
<name>Kuppuswamy Sathyanarayanan</name>
<email>sathyanarayanan.kuppuswamy@linux.intel.com</email>
</author>
<published>2025-11-21T00:05:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=1d6c915819f5b805c35487b6ce5923e31a28266b'/>
<id>1d6c915819f5b805c35487b6ce5923e31a28266b</id>
<content type='text'>
The current read_raw() implementation of the TPMI, MMIO and MSR
interfaces does not distinguish between atomic and non-atomic callers.

rapl_msr_read_raw() uses rdmsrq_safe_on_cpu(), which can sleep and
issue cross CPU calls. When MSR-based RAPL PMU support is enabled, PMU
event handlers can invoke this function from atomic context where
sleeping or rescheduling is not allowed. In atomic context, the caller
is already executing on the target CPU, so a direct rdmsrq() is
sufficient.

To support such usage, introduce an atomic flag to the read_raw()
interface to allow callers pass the context information. Modify the
common RAPL code to propagate this flag, and set the flag to reflect
the calling contexts.

Utilize the atomic flag in rapl_msr_read_raw() to perform direct MSR
read with rdmsrq() when running in atomic context, and a sanity check
to ensure target CPU matches the current CPU for such use cases.

The TPMI and MMIO implementations do not require special atomic
handling, so the flag is ignored in those paths.

This is a preparatory patch for adding MSR-based RAPL PMU support.

Signed-off-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
Reviewed-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
[ rjw: Subject tweak ]
Link: https://patch.msgid.link/20251121000539.386069-2-sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The current read_raw() implementation of the TPMI, MMIO and MSR
interfaces does not distinguish between atomic and non-atomic callers.

rapl_msr_read_raw() uses rdmsrq_safe_on_cpu(), which can sleep and
issue cross CPU calls. When MSR-based RAPL PMU support is enabled, PMU
event handlers can invoke this function from atomic context where
sleeping or rescheduling is not allowed. In atomic context, the caller
is already executing on the target CPU, so a direct rdmsrq() is
sufficient.

To support such usage, introduce an atomic flag to the read_raw()
interface to allow callers pass the context information. Modify the
common RAPL code to propagate this flag, and set the flag to reflect
the calling contexts.

Utilize the atomic flag in rapl_msr_read_raw() to perform direct MSR
read with rdmsrq() when running in atomic context, and a sanity check
to ensure target CPU matches the current CPU for such use cases.

The TPMI and MMIO implementations do not require special atomic
handling, so the flag is ignored in those paths.

This is a preparatory patch for adding MSR-based RAPL PMU support.

Signed-off-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
Reviewed-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
[ rjw: Subject tweak ]
Link: https://patch.msgid.link/20251121000539.386069-2-sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powercap: intel_rapl: Add support for Nova Lake processors</title>
<updated>2025-11-18T14:39:29+00:00</updated>
<author>
<name>Kaushlendra Kumar</name>
<email>kaushlendra.kumar@intel.com</email>
</author>
<published>2025-10-28T10:18:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=58075aec92a8141fd7f42e1c36d1bc54552c015e'/>
<id>58075aec92a8141fd7f42e1c36d1bc54552c015e</id>
<content type='text'>
Add RAPL support for Intel Nova Lake and Nova Lake L processors using
the core defaults configuration.

Signed-off-by: Kaushlendra Kumar &lt;kaushlendra.kumar@intel.com&gt;
[ rjw: Subject and changelog edits, rebase ]
Link: https://patch.msgid.link/20251028101814.3482508-1-kaushlendra.kumar@intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add RAPL support for Intel Nova Lake and Nova Lake L processors using
the core defaults configuration.

Signed-off-by: Kaushlendra Kumar &lt;kaushlendra.kumar@intel.com&gt;
[ rjw: Subject and changelog edits, rebase ]
Link: https://patch.msgid.link/20251028101814.3482508-1-kaushlendra.kumar@intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powercap: intel_rapl: Add support for Wildcat Lake platform</title>
<updated>2025-10-30T19:15:02+00:00</updated>
<author>
<name>Srinivas Pandruvada</name>
<email>srinivas.pandruvada@linux.intel.com</email>
</author>
<published>2025-10-23T17:45:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=39f421f2e301f995c17c35b783e2863155b3f647'/>
<id>39f421f2e301f995c17c35b783e2863155b3f647</id>
<content type='text'>
Add Wildcat Lake to the list of supported processors for RAPL.

Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Link: https://patch.msgid.link/20251023174532.1882008-1-srinivas.pandruvada@linux.intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add Wildcat Lake to the list of supported processors for RAPL.

Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Link: https://patch.msgid.link/20251023174532.1882008-1-srinivas.pandruvada@linux.intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powercap: intel_rapl_msr: Add PL4 support for Panther Lake</title>
<updated>2025-06-30T18:34:57+00:00</updated>
<author>
<name>Zhang Rui</name>
<email>rui.zhang@intel.com</email>
</author>
<published>2025-06-25T02:05:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=afc6a5b12b62c7743fb96fe27864604d7b33a5d2'/>
<id>afc6a5b12b62c7743fb96fe27864604d7b33a5d2</id>
<content type='text'>
Add Panther Lake to the list of processors where PL4 is supported.

Signed-off-by: Zhang Rui &lt;rui.zhang@intel.com&gt;
Link: https://patch.msgid.link/20250625020522.253548-1-rui.zhang@intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add Panther Lake to the list of processors where PL4 is supported.

Signed-off-by: Zhang Rui &lt;rui.zhang@intel.com&gt;
Link: https://patch.msgid.link/20250625020522.253548-1-rui.zhang@intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86/msr: Add explicit includes of &lt;asm/msr.h&gt;</title>
<updated>2025-05-02T08:23:47+00:00</updated>
<author>
<name>Xin Li (Intel)</name>
<email>xin@zytor.com</email>
</author>
<published>2025-05-01T05:42:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=efef7f184f2eaf29a1ca676712d0e6e851cd0191'/>
<id>efef7f184f2eaf29a1ca676712d0e6e851cd0191</id>
<content type='text'>
For historic reasons there are some TSC-related functions in the
&lt;asm/msr.h&gt; header, even though there's an &lt;asm/tsc.h&gt; header.

To facilitate the relocation of rdtsc{,_ordered}() from &lt;asm/msr.h&gt;
to &lt;asm/tsc.h&gt; and to eventually eliminate the inclusion of
&lt;asm/msr.h&gt; in &lt;asm/tsc.h&gt;, add an explicit &lt;asm/msr.h&gt; dependency
to the source files that reference definitions from &lt;asm/msr.h&gt;.

[ mingo: Clarified the changelog. ]

Signed-off-by: Xin Li (Intel) &lt;xin@zytor.com&gt;
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
Acked-by: Dave Hansen &lt;dave.hansen@linux.intel.com&gt;
Acked-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Acked-by: Ilpo Järvinen &lt;ilpo.jarvinen@linux.intel.com&gt;
Cc: Andy Lutomirski &lt;luto@kernel.org&gt;
Cc: Brian Gerst &lt;brgerst@gmail.com&gt;
Cc: Juergen Gross &lt;jgross@suse.com&gt;
Cc: H. Peter Anvin &lt;hpa@zytor.com&gt;
Cc: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Cc: Kees Cook &lt;keescook@chromium.org&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Borislav Petkov &lt;bp@alien8.de&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Josh Poimboeuf &lt;jpoimboe@redhat.com&gt;
Cc: Uros Bizjak &lt;ubizjak@gmail.com&gt;
Link: https://lore.kernel.org/r/20250501054241.1245648-1-xin@zytor.com
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For historic reasons there are some TSC-related functions in the
&lt;asm/msr.h&gt; header, even though there's an &lt;asm/tsc.h&gt; header.

To facilitate the relocation of rdtsc{,_ordered}() from &lt;asm/msr.h&gt;
to &lt;asm/tsc.h&gt; and to eventually eliminate the inclusion of
&lt;asm/msr.h&gt; in &lt;asm/tsc.h&gt;, add an explicit &lt;asm/msr.h&gt; dependency
to the source files that reference definitions from &lt;asm/msr.h&gt;.

[ mingo: Clarified the changelog. ]

Signed-off-by: Xin Li (Intel) &lt;xin@zytor.com&gt;
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
Acked-by: Dave Hansen &lt;dave.hansen@linux.intel.com&gt;
Acked-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Acked-by: Ilpo Järvinen &lt;ilpo.jarvinen@linux.intel.com&gt;
Cc: Andy Lutomirski &lt;luto@kernel.org&gt;
Cc: Brian Gerst &lt;brgerst@gmail.com&gt;
Cc: Juergen Gross &lt;jgross@suse.com&gt;
Cc: H. Peter Anvin &lt;hpa@zytor.com&gt;
Cc: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Cc: Kees Cook &lt;keescook@chromium.org&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Borislav Petkov &lt;bp@alien8.de&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Josh Poimboeuf &lt;jpoimboe@redhat.com&gt;
Cc: Uros Bizjak &lt;ubizjak@gmail.com&gt;
Link: https://lore.kernel.org/r/20250501054241.1245648-1-xin@zytor.com
</pre>
</div>
</content>
</entry>
<entry>
<title>x86/msr: Rename 'rdmsrl_safe_on_cpu()' to 'rdmsrq_safe_on_cpu()'</title>
<updated>2025-04-10T09:58:49+00:00</updated>
<author>
<name>Ingo Molnar</name>
<email>mingo@kernel.org</email>
</author>
<published>2025-04-09T20:28:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=5e404cb7ac4c097e95896a4a3fba5f5aabf7f679'/>
<id>5e404cb7ac4c097e95896a4a3fba5f5aabf7f679</id>
<content type='text'>
Suggested-by: "H. Peter Anvin" &lt;hpa@zytor.com&gt;
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
Acked-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Cc: Juergen Gross &lt;jgross@suse.com&gt;
Cc: Dave Hansen &lt;dave.hansen@intel.com&gt;
Cc: Xin Li &lt;xin@zytor.com&gt;
Cc: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Suggested-by: "H. Peter Anvin" &lt;hpa@zytor.com&gt;
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
Acked-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Cc: Juergen Gross &lt;jgross@suse.com&gt;
Cc: Dave Hansen &lt;dave.hansen@intel.com&gt;
Cc: Xin Li &lt;xin@zytor.com&gt;
Cc: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
