Pull more ARM SoC updates from Arnd Bergmann:
"These updates came in after I had already tagged the branches, but
they still seem appropriate for 6.0 and most of them were part of
linux-next through other trees.
- The reset controller tree adds one new driver for the TI TPS380x
power management chip and a few minor changes in other drivers
- Apple M1 now has a DT entry for the NVMe controller after the
driver was merged, and has a new mailing list in the MAINTAINERS
file.
- Fixes for USB on the Socionext Uniphier platforms and the network
controller on Intel Cyclone5"
* tag 'arm-late-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
arm64: dts: uniphier: Fix USB interrupts for PXs3 SoC
ARM: dts: uniphier: Fix USB interrupts for PXs2 SoC
arm64: dts: apple: t8103: Add ANS2 NVMe nodes
reset: tps380x: Fix spelling mistake "Voltags" -> "Voltage"
reset: tps380x: Add TPS380x device driver supprt
dt-bindings: reset: Add TPS380x documentation
dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G2UL USBPHY Control bindings
ARM: dts: add EMAC AXI settings for Cyclone5
reset: reset-simple should depends on HAS_IOMEM
Revert "reset: microchip-sparx5: allow building as a module"
reset: a10sr: allow building under COMPILE_TEST
reset: allow building of reset simple driver if expert config selected
reset: microchip-sparx5: allow building as a module
arm64: dts: apple: Re-parent ANS2 power domains
MAINTAINERS: add ARM/APPLE MACHINE mailing list
Pull SPDX updates from Greg KH: "Here is the set of SPDX comment updates for 6.0-rc1. Nothing huge here, just a number of updated SPDX license tags and cleanups based on the review of a number of common patterns in GPLv2 boilerplate text. Also included in here are a few other minor updates, two USB files, and one Documentation file update to get the SPDX lines correct. All of these have been in the linux-next tree for a very long time" * tag 'spdx-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx: (28 commits) Documentation: samsung-s3c24xx: Add blank line after SPDX directive x86/crypto: Remove stray comment terminator treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_406.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_398.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_391.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_390.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_385.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_319.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_318.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_298.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_292.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_179.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 2) treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 1) treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_160.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_152.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_149.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_147.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_133.RULE ...
There is a spelling mistake in the MODULE_DESCRIPTION text. Fix it. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220728110554.18320-1-colin.i.king@gmail.com
The TI TPS380x family [1] is a voltage supervisor with a dedicated manual reset (mr) line input and a reset output. The chip(s) have a build in reset delay, depending on the chip partnumber. This simple driver addresses this so the cosumer don't need to care about it. [1] https://www.ti.com/product/TPS3801 Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> [p.zabel@pengutronix.de: drop Todo comment about min/typ/max reset time] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220530092226.748644-2-m.felsch@pengutronix.de
The reset-simple driver does not build on all architecuters as it requires
devm_ioremap_resource() which is only built when CONFIG_HAS_IOMEM is enabled
in the kenrel. Fix the following error by depending on CONFIG_HAS_IOMEM:
drivers/reset/reset-simple.o: in function `reset_simple_probe':
reset-simple.c:(.text+0x3aa): undefined reference to `devm_ioremap_resource'
Fixes: 18d1909be345 ("reset: allow building of reset simple driver if expert config selected")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20220719085200.203688-1-ben.dooks@sifive.com
Merge the new SoC support from Tomer Maimon: "This patchset adds initial support for the Nuvoton Arbel NPCM8XX Board Management controller (BMC) SoC family. The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC. The NPCM8XX computing subsystem comprises a quadcore ARM Cortex A35 ARM-V8 architecture. This patchset adds minimal architecture and drivers such as: Clocksource, Clock, Reset, and WD. Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX. This patchset was tested on the Arbel NPCM8XX evaluation board." I'm leaving out the clk controller driver, which is still under review. * nuvoton/newsoc: arm64: defconfig: Add Nuvoton NPCM family support arm64: dts: nuvoton: Add initial NPCM845 EVB device tree arm64: dts: nuvoton: Add initial NPCM8XX device tree arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string dt-bindings: arm: npcm: Add maintainer reset: npcm: Add NPCM8XX support dt-bindings: reset: npcm: Add support for NPCM8XX reset: npcm: using syscon instead of device data ARM: dts: nuvoton: add reset syscon property dt-bindings: reset: npcm: add GCR syscon property dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock dt-bindings: watchdog: npcm: Add npcm845 compatible string dt-bindings: timer: npcm: Add npcm845 compatible string
Updated the NPCM reset driver to add support for Nuvoton BMC NPCM8XX SoC. As part of adding NPCM8XX support: - Add NPCM8XX specific compatible string. - Add NPCM8XX USB reset. - Add data to handle architecture-specific reset parameters. - Some of the Reset Id and number of resets are different from NPCM7XX. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Using syscon device tree property instead of device data to handle the NPCM general control registers. In case the syscon not found the code still search for nuvoton,npcm750-gcr to support DTS backward compatibility. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This reverts commit b6b9585876da018bdde2d5f15d206a689c0d70f3. This breaks MDIO on kswitch-d10, presumably because the global switch reset is not released early enough anymore. Reported-by: Michael Walle <michael@walle.cc> Cc: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220713084010.168720-1-p.zabel@pengutronix.de
This driver can be built under COMPILE_TEST. Allow it. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220711130624.1217599-1-p.zabel@pengutronix.de