linux-toradex.git/drivers/rtc, branch tegra-11.2.10 Linux kernel for Apalis and Colibri modules rtc : tps6586x: move NULL checking to the front. 2011-06-27T02:17:32+00:00 Jubeom Kim jubeomk@nvidia.com 2011-06-22T14:19:19+00:00 4299db4686321fb3017f9118a36610898f172639 Change-Id: Ic46e7f16fdd90db6dc8d7c1e723f10c5d928f382 Reviewed-on: http://git-master/r/37866 Tested-by: Jubeom Kim <jubeomk@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> 
Change-Id: Ic46e7f16fdd90db6dc8d7c1e723f10c5d928f382
Reviewed-on: http://git-master/r/37866
Tested-by: Jubeom Kim <jubeomk@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
rtc : tps6586x: avoid RTC time is getting slower 2011-04-20T04:01:40+00:00 Daehyoung Ko dko@nvidia.com 2011-04-11T20:04:54+00:00 2998ead828412c83de86e344f1c1e767bc01d7ca To ensure an accurate read of the RTC registers during the required multi-byte read operation, the PMU RTC is designed with the following protection scheme - A circuit detects a write/read and locks the RTC_COUNT4 value by keeping the RTC in a suspended mode - During the suspended mode, a secondary counter is used to keep track of all counts that would have normally incremented the RTC - After the read is complete, the value of the secondary counter is added back to the RTC registers and thereby keeping the RTC accurate - The backup counter allows for a 1ms RTC suspend mode duration when the RTC prescaler is enabled. i2c needs to generate a 2 msgs when reading. - the address setup(write RTC_COUNT4 operation), hence start locking the RTC_COUNT4 - the data transfer (read RTC_COUNT4 operation),release locking it. this may allow the CPU to execute other portions of code in between the two operation. The fix is to start a PMU RTC access by reading the register prior to the RTC_COUNT4 so that access of the RTC PMU registers will be guaranteed to always occur within the 1ms time period. - the address setup(write RTC_COUNT4-1 operation), so there is no locking the RTC_COUNT4 - the data transfer (read RTC_COUNT4 operation), starting locking the RTC_COUNT4 and release locking the RTC_COUNT4 in one operation, so it will be guaranteed within 1ms Bug 811075 Change-Id: Ie07472a329f6a0eed11e6a039cd93307bb5276a0 Reviewed-on: http://git-master/r/27537 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> 
To ensure an accurate read of the RTC registers during the required
multi-byte read operation, the PMU RTC is designed with the following
protection scheme

- A circuit detects a write/read and locks the RTC_COUNT4 value
by keeping the RTC in a suspended mode

- During the suspended mode, a secondary counter is used to
keep track of all counts that would have normally incremented the RTC

- After the read is complete, the value of the secondary counter is
added back to the RTC registers and thereby keeping the RTC accurate

- The backup counter allows for a 1ms RTC suspend mode duration
when the RTC prescaler is enabled.

i2c needs to generate a 2 msgs when reading.
  - the address setup(write RTC_COUNT4 operation),
hence start locking the RTC_COUNT4
  - the data transfer (read RTC_COUNT4 operation),release locking it.
this may allow the CPU to execute other portions of code
in between the two operation.

The fix is to start a PMU RTC access by reading the register prior to
the RTC_COUNT4 so that access of the RTC PMU registers will be guaranteed
to always occur within the 1ms time period.
  - the address setup(write RTC_COUNT4-1 operation),
so there is no locking the RTC_COUNT4
  - the data transfer (read RTC_COUNT4 operation),
starting locking the RTC_COUNT4 and release locking the RTC_COUNT4
in one operation, so it will be guaranteed within 1ms

Bug 811075

Change-Id: Ie07472a329f6a0eed11e6a039cd93307bb5276a0
Reviewed-on: http://git-master/r/27537
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
rtc: tps6586x RTC clock fix 2011-04-15T04:22:15+00:00 Andre Sihera asihera@nvidia.com 2011-04-08T03:37:11+00:00 d6ad1d95125bf21ed6c99cc8a633f0a23779d18a Specified OSC_SRC_SEL flag to force clock signal to be taken from an externally generated source rather than be calculated internally. This should raise the accuracy to within +/-2 seconds/24 hours. Bug 811075 Bug 810537 Change-Id: I7b7c4e4d752fdc03b81239f362a1d6f7aa4d3b92 Reviewed-on: http://git-master/r/27222 Reviewed-by: Andre Sihera <asihera@nvidia.com> Tested-by: Andre Sihera <asihera@nvidia.com> Reviewed-by: David Schalig <dschalig@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com> 
Specified OSC_SRC_SEL flag to force clock signal to be taken from
an externally generated source rather than be calculated internally.
This should raise the accuracy to within +/-2 seconds/24 hours.

Bug 811075
Bug 810537

Change-Id: I7b7c4e4d752fdc03b81239f362a1d6f7aa4d3b92
Reviewed-on: http://git-master/r/27222
Reviewed-by: Andre Sihera <asihera@nvidia.com>
Tested-by: Andre Sihera <asihera@nvidia.com>
Reviewed-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
[TPS658x RTC] Correct reg RTC_CTRL usage 2011-03-18T05:20:32+00:00 David Schalig dschalig@nvidia.com 2011-03-10T12:49:33+00:00 3da45a03a1af70e308592727ac134ce9d30d6b0f Correct PRE_BYPASS (clock scaler 32kHz/1kHz select) bitfield. Add platform data to tune RTC XTAL capacitance in board file. Bug 798832, Tested on Ventana/wake via Alarm Clock Change-Id: I82d67610a815866707fc1db934d7d4d7cf93d883 Reviewed-on: http://git-master/r/22402 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Reviewed-by: David Schalig <dschalig@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> 
Correct PRE_BYPASS (clock scaler 32kHz/1kHz select) bitfield.

Add platform data to tune RTC XTAL capacitance in board file.

Bug 798832, Tested on Ventana/wake via Alarm Clock

Change-Id: I82d67610a815866707fc1db934d7d4d7cf93d883
Reviewed-on: http://git-master/r/22402
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Reviewed-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
max8907c rtc: support wake alarms 2011-03-03T18:39:42+00:00 Tom Cherry tcherry@nvidia.com 2011-02-18T21:38:48+00:00 715a591214008391fe40fccca49ba133ac89dbf5 This change allows rtc alarms to wake the system. Change-Id: I2a7212fe7cc02b08893fe3a37824b0d39a9f5386 Reviewed-on: http://git-master/r/20101 Tested-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> 
This change allows rtc alarms to wake the system.

Change-Id: I2a7212fe7cc02b08893fe3a37824b0d39a9f5386
Reviewed-on: http://git-master/r/20101
Tested-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
rtc: tps6586x: avoid enabling/disabling of same irq 2011-02-09T02:20:42+00:00 Varun Wadekar vwadekar@nvidia.com 2011-02-08T05:15:39+00:00 23340cbd27bc002868c295f5b94eeccb903deb0f alarm_irq_enable can enable/disable irqs and the same irq will be enabled/disabled in set_alarm. Bug 770380 Change-Id: Ibd006e83028cea5cd251d789d258a5549bfa34ce Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/18661 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> 
alarm_irq_enable can enable/disable irqs and the same irq will
be enabled/disabled in set_alarm.

Bug 770380

Change-Id: Ibd006e83028cea5cd251d789d258a5549bfa34ce
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/18661
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
rtc: tps6586x: enable irqs while settings alarms 2011-02-08T02:15:29+00:00 Varun Wadekar vwadekar@nvidia.com 2011-02-07T14:29:33+00:00 1dea1254172ba7d8db550fbee5f525b363cbedab Bug 770380 Change-Id: I8950a3ef2259b233b1711b266fa7d29270d95bfd Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/18565 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> 
Bug 770380

Change-Id: I8950a3ef2259b233b1711b266fa7d29270d95bfd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/18565
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
max8907c RTC driver 2011-02-05T02:16:43+00:00 Tom Cherry tcherry@nvidia.com 2011-01-21T22:38:45+00:00 21f5bc602a71c41e5c281265b2491d1593a90b85 Initial checkin for Maxim max8907c RTC driver Change-Id: I764440cc1b0410e54f480a6e0ce424103052df14 Reviewed-on: http://git-master/r/16615 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> 
Initial checkin for Maxim max8907c RTC driver

Change-Id: I764440cc1b0410e54f480a6e0ce424103052df14
Reviewed-on: http://git-master/r/16615
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
mfd: tps6586x: fix alarm1 support 2011-02-03T01:20:44+00:00 Varun Wadekar vwadekar@nvidia.com 2011-02-02T05:26:49+00:00 7184d208813f73be5e53e5c9b001be43e29bad52 instead of clearing the irq for alarm enable/disable, the proper bit in RTC_CONFIG has to be set/cleared. tps6586 does not support 1/sec update counter so remove support for update_irq_enable. replace it with alarm_irq_enable. Change-Id: Iee66a6625e810169253a750faf3f12d20d65d7d9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/17990 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> 
instead of clearing the irq for alarm enable/disable,
the proper bit in RTC_CONFIG has to be set/cleared.
tps6586 does not support 1/sec update counter so
remove support for update_irq_enable. replace it with
alarm_irq_enable.

Change-Id: Iee66a6625e810169253a750faf3f12d20d65d7d9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/17990
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Revert "alarm: disable rtc alarm suspend/resume handlers" 2011-01-28T01:18:47+00:00 Nitin Kumbhar nkumbhar@nvidia.com 2011-01-27T09:15:07+00:00 170d80909110ad7d437bccc9bffe9bbed32599fc This reverts commit 0f04e9f691396f4d1e4288fff91ae8f5862dbba3. Enable rtc alarm suspend/resume handlers which were disabled as WAR. BUG 773133 Change-Id: I666fdf92cb716b247eea1933d837f4c2439cd6fd Reviewed-on: http://git-master/r/17179 Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> 
This reverts commit 0f04e9f691396f4d1e4288fff91ae8f5862dbba3.
Enable rtc alarm suspend/resume handlers which were disabled
as WAR.

BUG 773133

Change-Id: I666fdf92cb716b247eea1933d837f4c2439cd6fd
Reviewed-on: http://git-master/r/17179
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>