linux-toradex.git/drivers/serial, branch tegra-10.8.3 Linux kernel for Apalis and Colibri modules [arm/tegra] serial: Using double buffering in receive path. 2010-08-27T18:50:38+00:00 Laxman Dewangan ldewangan@nvidia.com 2010-08-19T11:48:43+00:00 bccaf58c73b6b9bb726b87b18d6e3b5d2b6e1106 To improve the performance in receive path, the uart configures the dma in the continuous double buffering mode. The dma keep filling the same buffer in continuously and inform uart driver when half of buffer completes. Change-Id: Iff7c9433766f272384fc1a329ff1db8031987544 Reviewed-on: http://git-master/r/4419 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> 
To improve the performance in receive path, the uart configures
the dma in the continuous double buffering mode. The dma keep
filling the same buffer in continuously and inform uart driver
when half of buffer completes.

Change-Id: Iff7c9433766f272384fc1a329ff1db8031987544
Reviewed-on: http://git-master/r/4419
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
[arm/tegra] Serial: Confirming configured baudrate. 2010-08-17T07:35:54+00:00 Laxman Dewangan ldewangan@nvidia.com 2010-08-10T11:51:20+00:00 6538f1285df4f8c0381b9995d8fd74b866119ebe Sometimes, in uart, the desired baudrate can not be configured in 5% error accuracy due to not finding the correct combination of clock source freq and integer divisor. In this case the driver should generate the error message. Change-Id: Iafe245876a2cb9810c1025c02a4b6a36eb26aa4c Reviewed-on: http://git-master/r/4974 Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> 
Sometimes, in uart, the desired baudrate can not be configured
in 5% error accuracy due to not finding the correct combination
of clock source freq and integer divisor. In this case the driver
should generate the error message.

Change-Id: Iafe245876a2cb9810c1025c02a4b6a36eb26aa4c
Reviewed-on: http://git-master/r/4974
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
[arm/tegrar]serial:Make sure dma status updated before dma stop. 2010-08-06T21:10:01+00:00 Laxman Dewangan ldewangan@nvidia.com 2010-08-06T01:15:44+00:00 1d37d0aa2e3dc546736430479053cf12c59011e7 Sometimes, when uart ask for the dma for get the number of bytes transferred by dma, the dma does not return the actual number of bytes transffred, it returns the less number of byes (less by burst size) and so uart driver client gets the data loss in communication. So to avoid the race condition, the driver stops the incoming data by making RTS line to inactive and wait for some time to complete the dma burst and then ask dma to get number of bytes transffred by dma from fifo to memory. Change-Id: I08de955fde77431115626bd884b68c8e42d52270 Reviewed-on: http://git-master/r/4832 Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> 
Sometimes, when uart ask for the dma for get the number of bytes
transferred by dma, the dma does not return the actual number of
bytes transffred, it returns the less number of byes (less by
burst size) and so uart driver client gets the data loss in
communication.

So to avoid the race condition, the driver stops the incoming data
by making RTS line to inactive and wait for some time to complete
the dma burst and then ask dma to get number of bytes transffred
by dma from fifo to memory.

Change-Id: I08de955fde77431115626bd884b68c8e42d52270
Reviewed-on: http://git-master/r/4832
Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
[arm/tegra] Serial: Fixing tx trigger level setting. 2010-08-05T22:55:24+00:00 Laxman Dewangan ldewangan@nvidia.com 2010-08-04T08:35:53+00:00 c20ab04377ad15f9326a02000326d01a01a12df4 On tegra uart, the FCR setting for different tx trigger level is not same as the 16550 tx trigger level setting. The tegra uart have the setting in reverse direction on tx fifo attention level: b00 for 16 bytes attention level. b01 for 8 byte attention level. b10 for 4 byte attention level b11 for 1 byte attention level. The rx trigger attention level match with the standard uart FCR register setttings. Also fixing the typo in code when setting DTR. bug 717072 Change-Id: I3e5230de71652e3216949734f4eaca8b85e03d99 Reviewed-on: http://git-master.nvidia.com/r/4753 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> 
On tegra uart, the FCR setting for different tx trigger level
is not same as the 16550 tx trigger level setting. The tegra
uart have the setting in reverse direction on tx fifo attention
level:
b00 for 16 bytes attention level.
b01 for 8 byte attention level.
b10 for 4 byte attention level
b11 for 1 byte attention level.

The rx trigger attention level match with the standard uart
FCR register setttings.

Also fixing the typo in code when setting DTR.

bug 717072

Change-Id: I3e5230de71652e3216949734f4eaca8b85e03d99
Reviewed-on: http://git-master.nvidia.com/r/4753
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
[arm/tegra] serial: write accessor should not add read ops. 2010-08-04T15:51:22+00:00 Laxman Dewangan ldewangan@nvidia.com 2010-08-04T06:06:08+00:00 25a04a4278106ad5925795a7dc855e7335a18ceb The write accessor function uart_writeb() and uart_writel() is doing the read of the same address on which it is writing the data. This is causing unnecessarily read of rx fifo and so causing data loss in rx path if tx fifo is getting written by cpu. This is happening becasue of rx fifo and tx fifo address are same. Change-Id: I194363872d0fd251ddd15a40f42e58acd5ccc7a1 Reviewed-on: http://git-master/r/4746 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> 
The write accessor function uart_writeb() and uart_writel() is
doing the read of the same address on which it is writing the data.
This is causing unnecessarily read of rx fifo and so causing data
loss in rx path if tx fifo is getting written by cpu. This is
happening becasue of rx fifo and tx fifo address are same.

Change-Id: I194363872d0fd251ddd15a40f42e58acd5ccc7a1
Reviewed-on: http://git-master/r/4746
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
[arm/tegra] serial: Removing tx fifo empty wait after each tx. 2010-07-13T19:36:08+00:00 Laxman Dewangan ldewangan@nvidia.com 2010-07-11T09:46:58+00:00 93513be66fbc0770f849d0a6996692d50a923525 When dma is used to transmit the data through uart, there is a wait to become the tx fifo empty after each tx dma complete. This wait is not required after each dma transfer complete because the next dma/pio based transfer can start even if tx fifo is not empty. Th uart controller only req dma when there is space in tx fifo. The correct state will be returned from the function of tx_empty based on tx state and fifo status. Change-Id: I3eb34e26d68b8a3d214759c23b89ef6585881729 Reviewed-on: http://git-master.nvidia.com/r/3782 Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> 
When dma is used to transmit the data through uart, there is a wait
to become the tx fifo empty after each tx dma complete.
This wait is not required after each dma transfer complete because
the next dma/pio based transfer can start even if tx fifo is not
empty. Th uart controller only req dma when there is space in tx
fifo.

The correct state will be returned from the function of tx_empty
based on tx state and fifo status.

Change-Id: I3eb34e26d68b8a3d214759c23b89ef6585881729
Reviewed-on: http://git-master.nvidia.com/r/3782
Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
[arm/tegra] serial: Enabling hw based rts control. 2010-07-09T16:48:49+00:00 Laxman Dewangan ldewangan@nvidia.com 2010-06-28T17:02:04+00:00 dcea9bbb855b9fcb34371ff4d021d5095adb5d4a Tegra arch2x have the capability to control the rts line based on data available in the rx fifo. If data vaiable in rx fifo is equal to the rx trigger level then rts become inactive by the controller. Once the data read from fifo either by cpu or by the dma, the rts become active by hw. Change-Id: I67a52ea105973e9ca21a4cc08f0fb1e3234a7d55 Reviewed-on: http://git-master/r/3299 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> 
Tegra arch2x have the capability to control the rts line based on
data available in the rx fifo. If data vaiable in rx fifo is equal
to the rx trigger level then rts become inactive by the controller.
Once the data read from fifo either by cpu or by the dma, the rts
become active by hw.

Change-Id: I67a52ea105973e9ca21a4cc08f0fb1e3234a7d55
Reviewed-on: http://git-master/r/3299
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Tegra odm uart: add odm call-backs in uart driver 2010-06-29T02:10:22+00:00 Rui Zhuo rzhuo@nvidia.com 2010-06-28T08:57:03+00:00 0bd55d98d414bebbc5022229c27aa17e875c0331 Adding NVODM UART callbacks into linux uart driver so that customer can customized UART according to their actual usecases. Hook four NVODM UART functions in linux uart driver: NvOdmUartOpen, NvOdmUartClose, NvOdmUartSuspend, NvOdmUartResume. Bug 684390. Change-Id: I8f1a89122a57e14631efe876cb7e7bd4a35b73cd Reviewed-on: http://git-master/r/2817 Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com> 
Adding NVODM UART callbacks into linux uart driver so that customer
can customized UART according to their actual usecases.
Hook four NVODM UART functions in linux uart driver:
NvOdmUartOpen, NvOdmUartClose, NvOdmUartSuspend, NvOdmUartResume.
Bug 684390.

Change-Id: I8f1a89122a57e14631efe876cb7e7bd4a35b73cd
Reviewed-on: http://git-master/r/2817
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
[ARM/tegra]Serial:Check xmit buffer before updating xmit fifo 2010-06-23T05:47:23+00:00 Suresh Mangipudi smangipudi@nvidia.com 2010-06-22T10:15:32+00:00 a2f6d4d0337a6c67335404c4140bab95a53d8336 Checking explicitly number of available bytes in transmit buffer before writing into the transmit buffer. Removing additional checks. Bug 700035 Change-Id: Ica2a6649e9acb2e059ebf6bb08dc5eaecdad8ed7 Reviewed-on: http://git-master/r/2990 Tested-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> 
Checking explicitly number of available bytes in transmit buffer
before writing into the transmit buffer. Removing additional checks.

Bug 700035

Change-Id: Ica2a6649e9acb2e059ebf6bb08dc5eaecdad8ed7
Reviewed-on: http://git-master/r/2990
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
[arm/tegra]serial: Power control api for bluesleep power management. 2010-06-18T21:35:48+00:00 Laxman Dewangan ldewangan@nvidia.com 2010-06-17T08:46:19+00:00 98e7f2cfa2fa0a62bf09e04a90719f04a8472588 Adding apis for following function to hooking up tegra serial driver with bluesleep power management: - Clock off. - Clock on. - Setting flow control to desired state. - Checking for tx fifo status. Following 4 state of uart state machine is developed to achieve this: UART_CLOSED, UART_OPENED, UART_SUSPEND, UART_CLOCK_OFF. The transitions of states are as follows: UART_CLOSED: the init state on which resource is allocated but not opened by client or when device is closed. UART_OPENED: Able to do data transfer. CLOSED to OPENED by opening the port. CLOCK_OFF to OPENED by calling function tegra_uart_request_clock_on(). SUSPEND to OPENED by calling resume(). UART_CLOCK_OFF: The controller clock is disabled and so no data transfer can happen. At this state, controller is not ready for deep power down. OPENED to CLOCK_OFF by calling tegra_uart_request_clock_off(). Can not go to this state from CLOSED and SUSPEND. UART_SUSPEND: The controller is in suspended state and ready for deep power down. UART_CLOCK_OFF to SUSPEND: OPENED to SUSPEND. Change-Id: Ib0c40547665181cadd172840be9aed2cc18ba448 Reviewed-on: http://git-master/r/2819 Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> 
Adding apis for following function to hooking up tegra serial driver with
bluesleep power management:
- Clock off.
- Clock on.
- Setting flow control to desired state.
- Checking for tx fifo status.

Following 4 state of uart state machine is developed to achieve this:
UART_CLOSED, UART_OPENED, UART_SUSPEND, UART_CLOCK_OFF.

The transitions of states are as follows:
UART_CLOSED: the init state  on which resource is allocated but not
             opened by client or when device is closed.

UART_OPENED: Able to do data transfer.
             CLOSED  to  OPENED by opening the port.
             CLOCK_OFF to OPENED by calling function tegra_uart_request_clock_on().
             SUSPEND to OPENED by calling resume().

UART_CLOCK_OFF: The controller clock is disabled and so no data transfer
                can happen. At this state, controller is not ready for
                deep power down.
             OPENED to CLOCK_OFF by calling tegra_uart_request_clock_off().
             Can not go to this state from CLOSED and SUSPEND.

UART_SUSPEND: The controller is in suspended state and ready for deep power down.
             UART_CLOCK_OFF to SUSPEND:
             OPENED to SUSPEND.

Change-Id: Ib0c40547665181cadd172840be9aed2cc18ba448
Reviewed-on: http://git-master/r/2819
Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>