Getting the transfer count by dma with rts disable. In this way we can avoid the race condition arise by hw with incoming data. Change-Id: Ieeeadfeea9293c70fd2eb96ff9d82888a58b2b3a Reviewed-on: http://git-master/r/11020 Tested-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
There is sysrq feature which works from console with sending break and then character. The console driver uses the 8250 driver. In tegra uart controller, after receiving break, it needs to clear the rx fifo by reading fifo till empty to receive the another break/character. Fixing this issue in 8250 driver. bug 697978 Change-Id: I4eb71a67bafc186ec9934fce164e28ad86fa0ace Reviewed-on: http://git-master/r/8736 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
Clean up warning message caused by unused variable and improper struct type. Bug 682070 Change-Id: I3409ad22e67252df14d6d14898aa8792a0019574 Reviewed-on: http://git-master/r/8436 Reviewed-by: Lance Zhao <lazhao@nvidia.com> Tested-by: Lance Zhao <lazhao@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
If serial core driver request for the stop rx then dequeue the dma request and read the rx fifo only if rx is in progress. Change-Id: I8cd8a75a59773f0195ed876f7faeb89ac0f2cbec Reviewed-on: http://git-master/r/7579 Reviewed-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
When system runs out of dma and uart driver tries to allocate dma, the dma allocation fails. In such case, the uart communication should work with interrupt based -non dma mode. bug 730003 (cherry picked from commit 4a9d5633474c806799ccc6d167f3d624c92d560c) (cherry picked from commit 2000a076103c559446d11ad49debc4e0f2952e8a) Change-Id: I96c2a3f79fd9044e3b54771b60cad7dcb12f517b Reviewed-on: http://git-master/r/6599 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Harry Hong <hhong@nvidia.com> Tested-by: Harry Hong <hhong@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Adding the valid pointer checks before accessing the pointers which is passed when public apis are called. Also resetting the pointers to null once the allocated handles are freed. (cherry picked from commit 0954407534a757b316bc35a0232968feed23243a) Change-Id: Ib8b99f0556fb9a98c74ba8911a00879451fad9e5 Reviewed-on: http://git-master/r/6578 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
When uart_close() or uart_suspend() calls the tegra_uart_suspend() the drivers waits in tight loop for tx to be empty. This wait is not required because serial_core driver have already waited for the tx fifo to empty with proper timeout before calling these function. bug 730612 (cherry picked from commit 13387c532dfb35dc672b290aec8b7a4db49730d6) (cherry picked from commit ddd896c933e3f8d5fb28948ad957ec12b3d881cd) Change-Id: Ie898ad0a134684844bf80ae00a1c8dd4b02a605a Reviewed-on: http://git-master/r/6372 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Harry Hong <hhong@nvidia.com> Tested-by: Harry Hong <hhong@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
To improve the performance in receive path, the uart configures the dma in the continuous double buffering mode. The dma keep filling the same buffer in continuously and inform uart driver when half of buffer completes. Change-Id: Iff7c9433766f272384fc1a329ff1db8031987544 Reviewed-on: http://git-master/r/4419 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Sometimes, in uart, the desired baudrate can not be configured in 5% error accuracy due to not finding the correct combination of clock source freq and integer divisor. In this case the driver should generate the error message. Change-Id: Iafe245876a2cb9810c1025c02a4b6a36eb26aa4c Reviewed-on: http://git-master/r/4974 Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
Sometimes, when uart ask for the dma for get the number of bytes transferred by dma, the dma does not return the actual number of bytes transffred, it returns the less number of byes (less by burst size) and so uart driver client gets the data loss in communication. So to avoid the race condition, the driver stops the incoming data by making RTS line to inactive and wait for some time to complete the dma burst and then ask dma to get number of bytes transffred by dma from fifo to memory. Change-Id: I08de955fde77431115626bd884b68c8e42d52270 Reviewed-on: http://git-master/r/4832 Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>