linux-toradex.git/drivers/serial, branch tegra-12r8-early Linux kernel for Apalis and Colibri modules Serial: tegra: Allow 2% error in selecting clock source for baudrate. 2011-09-02T04:11:34+00:00 Laxman Dewangan ldewangan@nvidia.com 2011-09-01T05:06:42+00:00 6d310aef62c5b1d11b44379d28766f20b1f3335d Allowing 2% error in calculated baudrate when finding the best clock source uart controller. bug 870388 Change-Id: Id765efd7bf087e10bc93a8ba5bd1eec8a8f3ef48 Reviewed-on: http://git-master/r/50255 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> 
Allowing 2% error in calculated baudrate when finding the best clock
source uart controller.

bug 870388

Change-Id: Id765efd7bf087e10bc93a8ba5bd1eec8a8f3ef48
Reviewed-on: http://git-master/r/50255
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
serial: tegra: Avoid schedule while atomic error 2011-08-30T00:25:37+00:00 Pradeep Goudagunta pgoudagunta@nvidia.com 2011-08-26T10:36:11+00:00 9ce011627ad7255153cf78d2c7e5b09a21d16101 Avoid schedule while atomic error backtrace while setting termios, by giving back lock taken before calling api which internally requests mutex lock. Bug 867218 Change-Id: I43afed41856c0b23324a1a5280c7e7963600d2e3 Reviewed-on: http://git-master/r/49431 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> 
Avoid schedule while atomic error backtrace while setting termios, by
giving back lock taken before calling api which internally requests
mutex lock.

Bug 867218

Change-Id: I43afed41856c0b23324a1a5280c7e7963600d2e3
Reviewed-on: http://git-master/r/49431
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
serial: tegra: Avoid lock in tx dma abort callback 2011-08-24T23:38:32+00:00 Laxman Dewangan ldewangan@nvidia.com 2011-08-22T06:41:35+00:00 c7ce0be1e96e9ad1722479f54abc3d30998fd39a If tx dma is aborted due to some reason like flush buffer, avoiding lock in tx dma complete callback to avoid the recursive locking. The caller have already hold the lock in this case. bug 860574 Change-Id: Iac63fb89ba03a3a89f55b43e823526ecf09d8a1f Reviewed-on: http://git-master/r/48420 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> 
If tx dma is aborted due to some reason like flush buffer, avoiding
lock in tx dma complete callback to avoid the recursive locking.
The caller have already hold the lock in this case.

bug 860574

Change-Id: Iac63fb89ba03a3a89f55b43e823526ecf09d8a1f
Reviewed-on: http://git-master/r/48420
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
serial: tegra: Add check for uart state before access 2011-08-13T00:36:59+00:00 Pradeep Goudagunta pgoudagunta@nvidia.com 2011-08-12T10:30:38+00:00 c34df94c603182403bccf7e3c00482db3c1204d1 Add proper check for uart state in public api to make sure client driver would not access UART registers when it is in invalid state. Bug 827693 Change-Id: Icfaed824d98023206dacd0346a90e34f2fc6935e Reviewed-on: http://git-master/r/46923 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> 
Add proper check for uart state in public api to make sure client
driver would not access UART registers when it is in invalid state.

Bug 827693

Change-Id: Icfaed824d98023206dacd0346a90e34f2fc6935e
Reviewed-on: http://git-master/r/46923
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Revert "serial: tegra: Add delay after TX DMA complete" 2011-08-12T02:07:09+00:00 Pradeep Goudagunta pgoudagunta@nvidia.com 2011-08-11T07:10:42+00:00 7452cf3cccd8e0b1815716d5c0f15af55bd2d497 This reverts commit c445fc0003baa2abead2db1e38e8dab242ba26de. Reverting this change according to the ASIC recommendations. Bug 847599 Change-Id: I81156a57092b0e3043abc15310ce1d544c64b6f1 Reviewed-on: http://git-master/r/46592 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> 
This reverts commit c445fc0003baa2abead2db1e38e8dab242ba26de.
Reverting this change according to the ASIC recommendations.

Bug 847599

Change-Id: I81156a57092b0e3043abc15310ce1d544c64b6f1
Reviewed-on: http://git-master/r/46592
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
serial: tegra: Check tx fifo status before writing 2011-08-10T23:04:14+00:00 Pradeep Goudagunta pgoudagunta@nvidia.com 2011-08-10T12:09:51+00:00 fa1a2809608379d9c839700c83c2b3cce4c83392 TX fifo should be checked before writing into it, if it is full then stop writing. Bug 847599 Change-Id: I12c654e3709fe42ec3494d90ac4fa256a790e9b5 Reviewed-on: http://git-master/r/46351 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> 
TX fifo should be checked before writing into it, if it is full then stop
writing.

Bug 847599

Change-Id: I12c654e3709fe42ec3494d90ac4fa256a790e9b5
Reviewed-on: http://git-master/r/46351
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
serial: tegra: Add delay after TX DMA complete 2011-08-05T18:15:21+00:00 Pradeep Goudagunta pgoudagunta@nvidia.com 2011-08-04T06:04:12+00:00 c445fc0003baa2abead2db1e38e8dab242ba26de Add 30 micro seconds delay after TX DMA burst complete, to make sure DMA burst completed before writing to tx fifo. Bug 847599 Change-Id: Ifcc1f3f208f8c2396ef410bedfa1158643b94015 Reviewed-on: http://git-master/r/44933 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Tested-by: Om Prakash Singh <omp@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> 
Add 30 micro seconds delay after TX DMA burst complete, to make
sure DMA burst completed before writing to tx fifo.

Bug 847599

Change-Id: Ifcc1f3f208f8c2396ef410bedfa1158643b94015
Reviewed-on: http://git-master/r/44933
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Tested-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
serial: 8250: tegra: disabling MSR interrupts 2011-07-08T01:37:51+00:00 Pradeep Goudagunta pgoudagunta@nvidia.com 2011-07-06T10:48:46+00:00 d0814d03a1588d019d553c37ca8cf582b2e38cd3 -Disabling modem status interrupts for tegra based UART. -Removed duplicate declaration of PORT_TEGRA. Bug 840111 Change-Id: I926c200ce66e926186e5295bc1ead8c6ecf70891 Reviewed-on: http://git-master/r/39788 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Jack Zhou <jazhou@nvidia.com> Tested-by: Jack Zhou <jazhou@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Krishna Monian <kmonian@nvidia.com> 
-Disabling modem status interrupts for tegra based UART.
-Removed duplicate declaration of PORT_TEGRA.

Bug 840111

Change-Id: I926c200ce66e926186e5295bc1ead8c6ecf70891
Reviewed-on: http://git-master/r/39788
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Jack Zhou <jazhou@nvidia.com>
Tested-by: Jack Zhou <jazhou@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Krishna Monian <kmonian@nvidia.com>
serial: tegra: support auto control of RTS 2011-07-08T01:37:41+00:00 Pradeep Goudagunta pgoudagunta@nvidia.com 2011-07-01T09:06:50+00:00 cd65b29dfc380b2c407ae69b1d86a72e48ac2b1d Added support for auto control of RTS. Bug 825938 Change-Id: Ic5ffde2252ab0f0ffb9001994863f3d4ed5d1173 Reviewed-on: http://git-master/r/39356 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> 
Added support for auto control of RTS.

Bug 825938

Change-Id: Ic5ffde2252ab0f0ffb9001994863f3d4ed5d1173
Reviewed-on: http://git-master/r/39356
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
serial: tegra: Support for best clock source 2011-06-24T06:16:04+00:00 Laxman Dewangan ldewangan@nvidia.com 2011-06-21T10:38:08+00:00 03bd2760d2ee22b8905f929630e9aaa41018594a Finding the best clock source for uart controller which can generate the clock rate having minimum error between requested baudrate and configured baudrate. bug 837140 bug 836059 Change-Id: I4e751b238612a21d894ee8e6611886ab6e832a36 Reviewed-on: http://git-master/r/37635 Tested-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> 
Finding the best clock source for uart controller which can
generate the clock rate having minimum error between requested
baudrate and configured baudrate.

bug 837140
bug 836059

Change-Id: I4e751b238612a21d894ee8e6611886ab6e832a36
Reviewed-on: http://git-master/r/37635
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>