linux-toradex.git/drivers/serial, branch tegra-9.12.6 Linux kernel for Apalis and Colibri modules serial: Fix intermediate variable overflow 2010-02-11T03:12:48+00:00 Anantha Idapalapati aidapalapati@nvidia.com 2010-02-11T03:12:48+00:00 09634b1e6dc5cccb2bee313981757978353f4595 tegra serial driver calculates the clock values based on baudrate requested. while calculating clock values for higher baud rates, the intermediate values are getting truncated because of 32-bit overflow. Redefining the intermediate variables to 64-bit(unsigned long long instead of unsigned long) is resolving the issue. 
tegra serial driver calculates the clock values based on baudrate requested.
while calculating clock values for higher baud rates, the intermediate
values are getting truncated because of 32-bit overflow. Redefining the
intermediate variables to 64-bit(unsigned long long instead of unsigned long)
is resolving the issue.
serial: Fix lock-up caused by the recursive calls to UART spin-lock 2010-02-10T06:59:10+00:00 Anantha Idapalapati aidapalapati@nvidia.com 2010-02-09T13:26:15+00:00 beaceeddee0cee9cffac428c8810fef0feb03bdf Replacing the spin_lock(), spin_unlock() functions used in ISR with spin_lock_irqsave(), spin_unlock_irqrequest() functions. Change-Id: Ib7639e3dc790c2b8471098b8a435d8800adae72c 
Replacing the spin_lock(), spin_unlock() functions used in ISR with
spin_lock_irqsave(), spin_unlock_irqrequest() functions.

Change-Id: Ib7639e3dc790c2b8471098b8a435d8800adae72c
tegra: Using dam_alloc_coherent instead of dma_alloc_writecombine. 2010-02-05T03:21:25+00:00 Venkata(Muni) Anda muni@nvidia.com 2010-02-05T03:21:25+00:00 8d899279f80a57fdbaceed2849a0033f8d118c0e Also Fixed a bug of ordering. Don't check for the FIFO is drained when the PIO is in flight. Change-Id: I0a0f81a2060f7f6a87dd8e5f6593d688c1c80d08 
Also Fixed a bug of ordering. Don't check for the FIFO is drained when the PIO is in flight.

Change-Id: I0a0f81a2060f7f6a87dd8e5f6593d688c1c80d08
tegra: Use write-combined DMA buffer for Tx DMA instead of zero-copy DMA. 2010-02-03T14:14:13+00:00 Venkata(Muni) Anda muni@nvidia.com 2010-01-29T18:53:33+00:00 2e054343da89c64413e5c08840fa7ce550a5e885 Given the constraints of Tx DMA to only use the dword aligned buffer start and dword aligned size, it would prudent to allocate a uncached DMA buffer and copy the data to that buffer before the trasmit. Main reason if Flushing L2 is not a cheap operation and the UART driver model is having to do all the operations while holding the spin-lock will not work. Change-Id: I0ca14d5809258e2a62111f0a8a5e8a8053de1a34 
Given the constraints of Tx DMA to only use the dword aligned buffer start
and dword aligned size, it would prudent to allocate a uncached DMA buffer
and copy the data to that buffer before the trasmit.

Main reason if Flushing L2 is not a cheap operation and the UART driver
model is having to do all the operations while holding the spin-lock
will not work.

Change-Id: I0ca14d5809258e2a62111f0a8a5e8a8053de1a34
tegra: Fix buges in DMA mode for high speed UART trasmit. 2010-01-29T03:06:25+00:00 Venkata(Muni) Anda muni@nvidia.com 2010-01-29T03:06:25+00:00 d380392a01015b6ee863e56e9a56f9a734fbea86 Mix of hardcoded values and enums caused the code to take unexepcted paths causing Tx failures. Tested with BT scanning of devices. Change-Id: Ic82f1749304262487a4bf0d2e42e5edeadcf360c 
Mix of hardcoded values and enums caused the code to take unexepcted paths causing Tx failures.

Tested with BT scanning of devices.

Change-Id: Ic82f1749304262487a4bf0d2e42e5edeadcf360c
tegra: Added suspend/resume functionality to native high speed serial driver. 2010-01-27T22:40:28+00:00 Venkata(Muni) Anda muni@nvidia.com 2010-01-27T22:19:12+00:00 bcfd153ff3bc6f6182388dce41204a3c5ec0e3f7 Tested with BT device after enabling the suspend ops driver. BT is working after multiple suspend/resume operations. Change-Id: I71f4c34f93e16c15e3f03676c3e5c9c5e84b43b9 
Tested with BT device after enabling the suspend ops driver.
BT is working after multiple suspend/resume operations.

Change-Id: I71f4c34f93e16c15e3f03676c3e5c9c5e84b43b9
tegra: Update the UART Tx data path and added new system DMA API. 2010-01-22T06:21:12+00:00 Venkata(Muni) Anda muni@nvidia.com 2010-01-21T20:24:41+00:00 5b340d629f24131fd5cffee7efa277ba5e1bd400 -Using workqueues instead of tasklets for Tx DMA. -Waiting for the FIFO to drain after the DMA is done, as it is apparently needed by the HW. - Added new DMA API to check if the req is already queued. Using tegra_dma_is_empty might not be correct as one DMA chanel can be serviced by multiple clients. With this change, i can browse the BT sometimes. It takes some retires to enable the BT. Also during the operation of the BT, i still see the messages like "out-of-order packet arrived" Don't know if this is an issue with ther UART or the BT protocol. Change-Id: I1502ad8178c3c95b4128c564c9f3c1d957195d46 
-Using workqueues instead of tasklets for Tx DMA.
-Waiting for the FIFO to drain after the DMA is done, as it is apparently
needed by the HW.
- Added new DMA API to check if the req is already queued. Using
  tegra_dma_is_empty might not be correct as one DMA chanel can be serviced
  by multiple clients.

With this change, i can browse the BT sometimes. It takes some retires to
enable the BT.

Also during the operation of the BT, i still see the messages like
"out-of-order packet arrived"

Don't know if this is an issue with ther UART or the BT protocol.

Change-Id: I1502ad8178c3c95b4128c564c9f3c1d957195d46
tegra: DMA driver and tegra serial driver updates. 2010-01-21T05:48:03+00:00 Venkata(Muni) Anda muni@nvidia.com 2010-01-15T09:35:56+00:00 de047f921798c652d90fa6bebe7b94b5047f42a2 DMA changes: - Channel lock should be taken in the ISR for making the DMA driver SMP safe. - In continous DMA mode,WCOUNT is the count of the half buffer not the full buffer. So, when updating the bytes received member of the req structure, received count should be accounted for appropriately. - Implemented the tegra_dma_flush() API. This API stops the DMA, resets the transfer status of the req in the head of the queue and reloads the req into the hardware if pending. - Added "threshold" callback. This is called when the buffer reaches the threshold. This is now aviable only for continous mode. Serial driver updates: - Simplifed the ISR handling in case of the DMA mode. - Using RTS to enable the flow control when dequeing and enqueing the DMA buffers. This will make sure that the sender will be flow controlled. This is still not working properly. - Added flush buffer call back - Called by serial core when the tx buffer is reset. - Fixed the locking at a couple of places, like ISR and shutdown callback. With these changes, i could able to use the BT sometimes. Sometimes i got parity errors. When I swtiched the Tx to PIO mode, BT worked fine. This can be done by changing the tx_force_pio global variable to 1. Change-Id: I4f738faac2fdb14622257878ef08db5397eebf8a 
DMA changes:
- Channel lock should be taken in the ISR for making the DMA driver SMP safe.
- In continous DMA mode,WCOUNT is the count of the half buffer not the full
buffer. So, when updating the bytes received member of the req structure,
received count should be accounted for appropriately.
- Implemented the tegra_dma_flush() API. This API stops the DMA, resets the
transfer status of the req in the head of the queue and reloads the req into
the hardware if pending.
- Added "threshold" callback. This is called when the buffer reaches the
  threshold. This is now aviable only for continous mode.

Serial driver updates:
- Simplifed the ISR handling in case of the DMA mode.
- Using RTS to enable the flow control when dequeing and enqueing the DMA
buffers. This will make sure that the sender will be flow controlled. This
is still not working properly.
- Added flush buffer call back - Called by serial core when the tx buffer is
reset.
- Fixed the locking at a couple of places, like ISR and shutdown callback.

With these changes, i could able to use the BT sometimes. Sometimes i got
parity errors.

When I swtiched the Tx to PIO mode, BT worked fine. This can be done by
changing the tx_force_pio global variable to 1.

Change-Id: I4f738faac2fdb14622257878ef08db5397eebf8a
tegra HS UART driver: Use PIO when DMA is not available. 2010-01-13T00:04:29+00:00 Venkata(Muni) Anda muni@nvidia.com 2010-01-11T23:10:26+00:00 db95f60980ce1367ffd4233583c49f2f59c10a8c Tested by pairing with BT devices in PIO mode. DMA mode is not working properly yet. Change-Id: I3328855354d4b2cd50da1ba30298cefc439beca8 
Tested by pairing with BT devices in PIO mode. DMA mode is not working
properly yet.

Change-Id: I3328855354d4b2cd50da1ba30298cefc439beca8
serial: compile fixes for tegra native serial driver 2010-01-09T02:41:25+00:00 Gary King gking@nvidia.com 2010-01-08T04:43:28+00:00 277f0cdec01d89637fa9f20dd7522ef504222fd7 when the serial driver was merged to git from perforce, some errors were introduced during the reformatting of it. these are now fixed. add a Kconfig to specify the maximum number of high-speed UARTs supported by the kernel, which will be used to ensure that enough DMA channels are reserved from the Tegra RM to allow the driver initialization to succeed Change-Id: I363a8375ebbdda004161672ff3700eb09be474ae 
when the serial driver was merged to git from perforce, some errors
were introduced during the reformatting of it. these are now fixed.

add a Kconfig to specify the maximum number of high-speed UARTs
supported by the kernel, which will be used to ensure that enough
DMA channels are reserved from the Tegra RM to allow the driver
initialization to succeed

Change-Id: I363a8375ebbdda004161672ff3700eb09be474ae