linux-toradex.git/drivers/serial, branch tegra-T30.ER5 Linux kernel for Apalis and Colibri modules arm: tegra: dma: Adding client name with dma allocation. 2011-04-26T22:56:18+00:00 Laxman Dewangan ldewangan@nvidia.com 2011-04-18T11:05:41+00:00 89aa98edfb250b54549580a6b0261a23af3d7c0c By changing the dma allocation API to take the client name, it is easy to track who is allocated the DMA channels when we run out of the DMA channels. Original-Change-Id: I016011cfd74089fed0da1bc0f121800017ce124a Reviewed-on: http://git-master/r/28031 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Change-Id: I048bcb87f95ee6d8ad2fdce993a1758dc5071666 
By changing the dma allocation API to take the client name, it is easy
to track who is allocated the DMA channels when we run out of the
DMA channels.

Original-Change-Id: I016011cfd74089fed0da1bc0f121800017ce124a
Reviewed-on: http://git-master/r/28031
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Change-Id: I048bcb87f95ee6d8ad2fdce993a1758dc5071666
i2c/serial: tegra: Fixing pointer check returned from clk_get 2011-04-26T22:55:55+00:00 Laxman Dewangan ldewangan@nvidia.com 2011-04-15T11:07:50+00:00 c0c090d57cab98ca1e6af4033e735b213f4d715a The clk_get() api returns valid pointer in case of scucess otherwise returns error pointer. Hence checking the retrun pointer using macro IS_ERR_OR_NULL() to detect any error. Original-Change-Id: I92a62dc2c22c243e2aa35d7a10f88b6170b02f34 Reviewed-on: http://git-master/r/27876 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I402141a3230b35292bdd31f9c0a7fb3bf261cbee 
The clk_get() api returns valid pointer in case of scucess otherwise
returns error pointer.
Hence checking the retrun pointer using macro IS_ERR_OR_NULL() to
detect any error.

Original-Change-Id: I92a62dc2c22c243e2aa35d7a10f88b6170b02f34
Reviewed-on: http://git-master/r/27876
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: I402141a3230b35292bdd31f9c0a7fb3bf261cbee
Update copyrights 2011-04-26T22:54:21+00:00 Scott Williams scwilliams@nvidia.com 2011-03-28T07:34:42+00:00 a0238cbd9709b5f1a4ccd9ed233f2335d48df023 Change-Id: I2ffeaf6f8dfeb279b40ca6f69f6c9157401a746a 
Change-Id: I2ffeaf6f8dfeb279b40ca6f69f6c9157401a746a
arm:tegra:uart: Set clk rate according to baudrate 2011-04-26T22:52:02+00:00 Pradeep Goudagunta pgoudagunta@nvidia.com 2011-02-11T10:55:43+00:00 51eac9019738240ca00e4f71923ba3f2703e9870 Adding support to hs_uart driver to set clock rate according to given baudrate. Original-Change-Id: Ia15421bf1db7f46f77b5d63c863703e441f1d3ff Reviewed-on: http://git-master/r/19233 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Tested-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Change-Id: I6d1beeb962f446eb0e169d8e316a39b9d7fe78e4 
Adding support to hs_uart driver to set clock rate  according to given
baudrate.

Original-Change-Id: Ia15421bf1db7f46f77b5d63c863703e441f1d3ff
Reviewed-on: http://git-master/r/19233
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: I6d1beeb962f446eb0e169d8e316a39b9d7fe78e4
arm: serial: tegra: Setting tx trigger level to 8 bytes 2011-04-26T22:51:00+00:00 Pradeep Goudagunta pgoudagunta@nvidia.com 2011-02-01T13:36:19+00:00 cfc6c36834dfea6d7ffb945b616d1542c204ea72 Changed transmit fcr trigger level and load size of serial8250 driver to 8 bytes. Bug : 785316 Original-Change-Id: I3aac46b05431d17a76c78fe062363af925b2835c Reviewed-on: http://git-master/r/17885 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Change-Id: If858d4aa86cc613dc0bbe7cb02c2d7d7778a941f 
Changed transmit fcr trigger level and load size of serial8250 driver
to 8 bytes.

Bug : 785316

Original-Change-Id: I3aac46b05431d17a76c78fe062363af925b2835c
Reviewed-on: http://git-master/r/17885
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: If858d4aa86cc613dc0bbe7cb02c2d7d7778a941f
[ARM] tegra:uart:Reseting Tx fifo in non fifo mode 2011-04-26T22:49:02+00:00 Pradeep Goudagunta pgoudagunta@nvidia.com 2010-12-17T10:45:05+00:00 252214ee4c4d3fea96fb2ca53e3f601a70f6c3a1 If Tx fifo is reset in fifo mode then extra bytes were seen in receiver end ASIC team recommended following as SW workaround -Disable fifo mode -Delay for 8x clock cycles -Reset Tx fifo -Enable fifo mode Bug : 742346 Original-Change-Id: Ia091d0050dd7137e874acc2948e517b76c0743b6 Reviewed-on: http://git-master/r/13610 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: Iebc31029adbe2b4d5d56403d09cf5636a5160262 
If Tx fifo is reset in fifo mode then extra bytes were seen in receiver end
ASIC team recommended following as SW workaround
-Disable fifo mode
-Delay for 8x clock cycles
-Reset Tx fifo
-Enable fifo mode

Bug : 742346

Original-Change-Id: Ia091d0050dd7137e874acc2948e517b76c0743b6
Reviewed-on: http://git-master/r/13610
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: Iebc31029adbe2b4d5d56403d09cf5636a5160262
[ARM/tegra] Add initial Tegra3 driver support 2011-04-26T22:48:27+00:00 Scott Williams scwilliams@nvidia.com 2010-12-07T19:13:31+00:00 464936c9afcab046e38fb8f7851627a7ac0520de Bug 764354 Original-Change-Id: I807433ff825bed1fe91ce0cf50a2b3691c64ef0a Reviewed-on: http://git-master/r/12227 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I3da91a438f98f2f51618446ce024f3fefd726a19 
Bug 764354

Original-Change-Id: I807433ff825bed1fe91ce0cf50a2b3691c64ef0a
Reviewed-on: http://git-master/r/12227
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: I3da91a438f98f2f51618446ce024f3fefd726a19
merging android-tegra-2.6.36 into git-master/linux-2.6/android-tegra-2.6.36 2011-04-01T11:30:08+00:00 Nitin Kumbhar nkumbhar@nvidia.com 2011-04-01T11:30:08+00:00 677368f44ce65fe2292f696f0bfd568d3ac78436 Conflicts: drivers/serial/tegra_hsuart.c drivers/usb/host/ehci-tegra.c Change-Id: Ief6c03a63615a41e85de59ad14dedef309d0b2fb 
Conflicts:
	drivers/serial/tegra_hsuart.c
	drivers/usb/host/ehci-tegra.c

Change-Id: Ief6c03a63615a41e85de59ad14dedef309d0b2fb
serial: 8250: support auto control of RTSCTS on tegra type 2011-03-29T06:49:40+00:00 Pradeep Goudagunta pgoudagunta@nvidia.com 2011-03-28T11:02:40+00:00 66fa9abefccdc75f6feb283ac60acacd257dcc99 Add UART_CAP_HW_CTSRTS flag to tegra type for supporting auto control of RTSCTS. Bug 803910 Change-Id: I7b69e4b203e66903ba5755338fcb55f4a87b9a43 Reviewed-on: http://git-master/r/24463 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> 
Add UART_CAP_HW_CTSRTS flag to tegra type for supporting auto control
of RTSCTS.

Bug 803910

Change-Id: I7b69e4b203e66903ba5755338fcb55f4a87b9a43
Reviewed-on: http://git-master/r/24463
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Merge branch 'linux-tegra-2.6.36' into android-tegra-2.6.36 2011-03-22T18:42:14+00:00 Colin Cross ccross@android.com 2011-03-22T18:42:14+00:00 9b571241de8cfa131178e9120ad46f1756bad8a7