linux-toradex.git/drivers/soc/qcom/llcc-qcom.c, branch v5.17

soc: qcom: llcc: Add configuration data for SM8350

2021-12-21T01:10:09+00:00

Add LLCC configuration data for SM8350 SoC.

Signed-off-by: Konrad Dybcio 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20211121002050.36977-2-konrad.dybcio@somainline.org

soc: qcom: llcc: Disable MMUHWT retention

2021-09-21T22:41:49+00:00

Disable MMUHWT retention for SC7280 as done for other platforms
to avoid more power burn.

Fixes: f6a07be63301 ("soc: qcom: llcc: Add configuration data for SC7280")
Signed-off-by: Naina Mehta 
Signed-off-by: Sai Prakash Ranjan 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20210921055942.30600-1-saiprakash.ranjan@codeaurora.org

soc: qcom: llcc: Add configuration data for SM6350

2021-09-21T22:41:47+00:00

Add LLCC configuration data for SM6350 SoC.

Reviewed-by: AngeloGioacchino Del Regno 
Signed-off-by: Konrad Dybcio 
Link: https://lore.kernel.org/r/20210820203105.229764-6-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson

soc: qcom: llcc: Add configuration data for SC7280

2021-03-12T02:22:20+00:00

Add LLCC configuration data for SC7280 SoC.

Signed-off-by: Sai Prakash Ranjan 
Link: https://lore.kernel.org/r/348fcb76ea837c043f2e493c6df8aa5ebb182c92.1614244789.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson

soc: qcom: llcc-qcom: Add support for SM8250 SoC

2020-12-28T18:15:14+00:00

SM8250 SoC uses LLCC IP version 2. In this version, the WRSC_EN register
needs to be written to enable the Write Sub Cache for each SCID. Hence,
use a dedicated "write_scid_en" member with predefined values and write
them for LLCC IP version 2.

Reviewed-by: Sai Prakash Ranjan 
Signed-off-by: Manivannan Sadhasivam 
Link: https://lore.kernel.org/r/20201130093924.45057-5-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson

soc: qcom: llcc-qcom: Extract major hardware version

2020-12-28T18:15:13+00:00

The major hardware version of the LLCC IP is encoded in its
LLCC_COMMON_HW_INFO register. Extract the version and cache it in the
driver data so that it can be used to implement version specific
functionality like enabling Write sub cache for given SCID.

Signed-off-by: Sai Prakash Ranjan 
[mani: splitted the version extract as a single patch and few cleanups]
Signed-off-by: Manivannan Sadhasivam 
Link: https://lore.kernel.org/r/20201130093924.45057-4-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson

soc: qcom: llcc: Add configuration data for SM8150

2020-11-20T04:22:25+00:00

Add LLCC configuration data for SM8150 SoC which controls
LLCC behaviour.

Signed-off-by: Souradeep Chowdhury 
Link: https://lore.kernel.org/r/957e3ae50c75720ef6227529d5ce3d4b457802e9.1601452132.git.schowdhu@codeaurora.org
Signed-off-by: Bjorn Andersson

soc: qcom: llcc-qcom: Fix expected kernel-doc formatting

2020-11-11T05:21:52+00:00

Kernel-doc expects struct documentation to start with 'struct '.

Fixes the following W=1 kernel build warning(s):

 drivers/soc/qcom/llcc-qcom.c:77: warning: cannot understand function prototype: 'struct llcc_slice_config '

Cc: Andy Gross 
Cc: Bjorn Andersson 
Cc: linux-arm-msm@vger.kernel.org
Reviewed-by: Bjorn Andersson 
Signed-off-by: Lee Jones 
Link: https://lore.kernel.org/r/20201103152838.1290217-21-lee.jones@linaro.org
Signed-off-by: Bjorn Andersson

soc: qcom: llcc: Support chipsets that can write to llcc

2020-10-26T14:53:53+00:00

Older chipsets may not be allowed to configure certain LLCC registers
as that is handled by the secure side software. However, this is not
the case for newer chipsets and they must configure these registers
according to the contents of the SCT table, while keeping in mind that
older targets may not have these capabilities. So add support to allow
such configuration of registers to enable capacity based allocation
and power collapse retention for capable chipsets.

Reason for choosing capacity based allocation rather than the default
way based allocation is because capacity based allocation allows more
finer grain partition and provides more flexibility in configuration.
As for the retention through power collapse, it has an advantage where
the cache hits are more when we wake up from power collapse although
it does burn more power but the exact power numbers are not known at
the moment.

Signed-off-by: Isaac J. Manjarres 
Reviewed-by: Douglas Anderson 
Reviewed-by: Stephen Boyd 
[saiprakash.ranjan@codeaurora.org: use existing config and reword commit msg]
Signed-off-by: Sai Prakash Ranjan 
Link: https://lore.kernel.org/r/dac7e11cf654fc6d75a6b5ca062ab87b01547810.1600151951.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson

soc: qcom: llcc: Move llcc configuration to its own function

2020-10-26T14:53:48+00:00

Cleanup qcom_llcc_cfg_program() by moving llcc configuration
to a separate function of its own. Also correct misspelled
'instance' caught by checkpatch.

Reviewed-by: Bjorn Andersson 
Reviewed-by: Stephen Boyd 
Suggested-by: Stephen Boyd 
Signed-off-by: Sai Prakash Ranjan 
Link: https://lore.kernel.org/r/51f9ad67333eedf326212dd1b040aade6978e5b1.1600151951.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson