linux-toradex.git/drivers/soc/renesas/Makefile, branch master

soc: renesas: Add Renesas R-Car MFIS driver

2026-05-04T09:58:54+00:00

Renesas R-Car MFIS offers multiple features but most importantly
mailboxes and hwspinlocks. Because they share a common register space
and a common register unprotection mechanism, a single driver was chosen
to handle all dependencies. (MFD and auxiliary bus have been tried as
well, but they failed because of circular dependencies.)

In this first step, the driver implements common register access and a
mailbox controller. hwspinlock support will be added incrementally, once
the subsystem allows out-of-directory drivers.

Signed-off-by: Kuninori Morimoto 
Signed-off-by: Wolfram Sang 
Acked-by: Jassi Brar 
Reviewed-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260402112709.13002-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven

soc: renesas: rz-sysc: Add SoC identification for RZ/G3L SoC

2026-03-06T12:40:12+00:00

Add SoC identification for the RZ/G3L SoC using the System Controller
(SYSC) block.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260203103031.247435-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

soc: renesas: Add support for RZ/N1 GPIO Interrupt Multiplexer

2026-01-15T11:05:16+00:00

On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those
interruption lines are multiplexed by the GPIO Interrupt Multiplexer in
order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.

The GPIO interrupt multiplexer IP does nothing but select 8 GPIO
IRQ lines out of the 96 available to wire them to the GIC input lines.

Signed-off-by: Herve Codina (Schneider Electric) 
Reviewed-by: Linus Walleij 
Tested-by: Wolfram Sang 
Reviewed-by: Wolfram Sang 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260114093938.1089936-8-herve.codina@bootlin.com
Signed-off-by: Geert Uytterhoeven

soc: renesas: rz-sysc: Add SoC identification for RZ/V2N SoC

2025-05-05T08:54:02+00:00

Add SoC identification for the RZ/V2N SoC using the System Controller
(SYS) block.

Signed-off-by: Lad Prabhakar 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/20250415085438.83856-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

soc: renesas: rz-sysc: Move RZ/V2H SoC detection to the SYS driver

2025-02-20T16:38:33+00:00

As per the other SoC variant of the same family, the system controller
provides SoC ID in its own registers.

Signed-off-by: John Madieu 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/20250128031342.52675-5-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

soc: renesas: rz-sysc: Add support for RZ/G3E family

2025-02-20T16:38:33+00:00

Add SoC detection support for the RZ/G3E SoC.  Also add support for
detecting the number of cores and the ETHOS-U55 NPU, and also detect PLL
mismatch for SW settings other than 1.7GHz.

Signed-off-by: John Madieu 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/20250128031342.52675-4-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

soc: renesas: rz-sysc: Move RZ/G3S SoC detection to the SYSC driver

2025-02-20T16:38:33+00:00

Now that we have SoC detection in the RZ SYSC driver, move the RZ/G3S
SoC detection to it. The SYSC provides SoC ID in its own registers.

Signed-off-by: Claudiu Beznea 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: John Madieu 
Link: https://lore.kernel.org/20250128031342.52675-3-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

soc: renesas: Add SYSC driver for Renesas RZ family

2025-02-20T16:38:33+00:00

The RZ/G3S system controller (SYSC) has various registers that control
different functionalities.  One of the exposed register offers
information about the SoC identification.

Add a driver that identifies the SoC.  Later the driver will be extended
with other functionalities.

Signed-off-by: Claudiu Beznea 
Signed-off-by: John Madieu 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/20250128031342.52675-2-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

soc: renesas: Move power-domain drivers to the genpd dir

2023-07-14T08:40:56+00:00

To simplify with maintenance let's move the renesas power-domain drivers to
the new genpd directory. Going forward, patches are intended to be managed
through a separate git tree, according to MAINTAINERS.

Cc: Geert Uytterhoeven 
Cc: Magnus Damm 
Cc: 
Signed-off-by: Ulf Hansson

soc: renesas: Add PWC support for RZ/V2M

2023-01-23T08:28:28+00:00

The Renesas RZ/V2M External Power Sequence Controller (PWC)
IP is capable of:
* external power supply on/off sequence generation
* on/off signal generation for the LPDDR4 core power supply (LPVDD)
* key input signals processing
* general-purpose output pins

Add the corresponding device driver.

Signed-off-by: Fabrizio Castro 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/r/20230106125816.10600-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven