linux-toradex.git/drivers/soc/sifive, branch master

soc: sifive: shunt ccache driver to drivers/cache

2023-11-22T11:49:25+00:00

Move the ccache driver over to drivers/cache, out of the drivers/soc
dumping ground, to this new collection point for cache controller
drivers.

Reviewed-by: Samuel Holland 
Tested-by: Samuel Holland 
Signed-off-by: Conor Dooley

soc: sifive: replace SOC_FOO with ARCH_FOO

2023-09-18T09:33:32+00:00

As part of unifiying what RISC-V calls microarch symbols to use
ARCH_, replace users of the SOC_ forms.

Signed-off-by: Conor Dooley

soc: sifive: ccache: Add StarFive JH7110 support

2022-12-26T22:50:15+00:00

This adds support for the StarFive JH7110 SoC which also
features this SiFive cache controller.

Signed-off-by: Emil Renner Berthing 
Signed-off-by: Hal Feng 
Signed-off-by: Conor Dooley

soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init()

2022-11-09T22:01:31+00:00

The device_node pointer returned by of_find_matching_node() with
refcount incremented, when finish using it, the refcount need be
decreased.

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang 
Reviewed-by: Conor Dooley 
Signed-off-by: Conor Dooley

soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()

2022-11-09T22:01:31+00:00

Add missing free_irq() before return error from sifive_ccache_init().

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang 
Reviewed-by: Conor Dooley 
Signed-off-by: Conor Dooley

soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()

2022-11-09T22:01:31+00:00

Add missing iounmap() before return error from sifive_ccache_init().

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang 
Reviewed-by: Conor Dooley 
Signed-off-by: Conor Dooley

soc: sifive: ccache: define the macro for the register shifts

2022-10-13T18:06:55+00:00

Define the macro for the register shifts, it could make the code be
more readable

Signed-off-by: Zong Li 
Reviewed-by: Conor Dooley 
Link: https://lore.kernel.org/r/20220913061817.22564-7-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt

soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes

2022-10-13T18:06:54+00:00

Use the pr_fmt() macro to prefix all the output with "CCACHE:"
to avoid having to write it out each time, or make a large diff
when the next change comes along.

Signed-off-by: Ben Dooks 
Signed-off-by: Zong Li 
Reviewed-by: Conor Dooley 
Link: https://lore.kernel.org/r/20220913061817.22564-6-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt

soc: sifive: ccache: reduce printing on init

2022-10-13T18:06:53+00:00

The driver prints out 6 lines on startup, which can easily be redcued
to two lines without losing any information.

Note, to make the types work better, uint64_t has been replaced with
ULL to make the unsigned long long match the format in the print
statement.

Signed-off-by: Ben Dooks 
Signed-off-by: Zong Li 
Reviewed-by: Conor Dooley 
Link: https://lore.kernel.org/r/20220913061817.22564-5-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt

soc: sifive: ccache: determine the cache level from dts

2022-10-13T18:06:52+00:00

Composable cache could be L2 or L3 cache, use 'cache-level' property of
device node to determine the level.

Signed-off-by: Zong Li 
Reviewed-by: Conor Dooley 
Link: https://lore.kernel.org/r/20220913061817.22564-4-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt