linux-toradex.git/drivers/spi/Kconfig, branch master Linux kernel for Apalis and Colibri modules spi: dw: Remove not-going-to-be-supported code for Baikal SoC 2026-01-29T11:54:47+00:00 Andy Shevchenko andriy.shevchenko@linux.intel.com 2026-01-27T21:05:41+00:00 da0a672268b34279aa999664860e6becc38f3f51 As noticed in the discussion [1] the Baikal SoC and platforms are not going to be finalized, hence remove stale code. Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1] Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260127210541.4068379-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org> 
As noticed in the discussion [1] the Baikal SoC and platforms
are not going to be finalized, hence remove stale code.

Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1]
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20260127210541.4068379-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: SPI_AXIADO should depend on ARCH_AXIADO 2026-01-27T22:36:15+00:00 Geert Uytterhoeven geert+renesas@glider.be 2026-01-27T19:08:31+00:00 e540be7d56d740144b1bd6f220b61ffe2f3830d4 The Axiado DB-H SPI controller is only present on Axiado AX3000 SoCs. Hence add a dependency on ARCH_AXIADO, to prevent asking the user about this driver when configuring a kernel without Axiado SoC Family support. Fixes: e75a6b00ad7962a7 ("spi: axiado: Add driver for Axiado SPI DB controller") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/386273d50fb3c51cccdba4b3101a0705208abd4d.1769540444.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org> 
The Axiado DB-H SPI controller is only present on Axiado AX3000 SoCs.
Hence add a dependency on ARCH_AXIADO, to prevent asking the user about
this driver when configuring a kernel without Axiado SoC Family support.

Fixes: e75a6b00ad7962a7 ("spi: axiado: Add driver for Axiado SPI DB controller")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/386273d50fb3c51cccdba4b3101a0705208abd4d.1769540444.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>
Axiado AX3000 SoC SPI DB controller driver 2026-01-13T14:02:17+00:00 Mark Brown broonie@kernel.org 2026-01-13T14:02:17+00:00 26cbb4dd58ae1ca83319e73e9397b06a8ca961c6 Merge series from Vladimir Moravcevic <vmoravcevic@axiado.com>: This series introduces new SPI controller driver for Axiado AX3000 SoC and its evaluation board. The SPI controller provides: - Full-duplex and half-duplex transfer support - Configurable clock polarity and phase - Interrupt-driven Functionality has been verified using the `jedec,spi-nor` interface to access onboard flash memory. This ensures compatibility with common NOR flash devices used in boot and storage subsystem. Further improvements, including performance tuning and extended hardware feature support, will be submitted in follow-up patches. 
Merge series from Vladimir Moravcevic <vmoravcevic@axiado.com>:

This series introduces new SPI controller driver for Axiado AX3000 SoC
and its evaluation board.

The SPI controller provides:
- Full-duplex and half-duplex transfer support
- Configurable clock polarity and phase
- Interrupt-driven

Functionality has been verified using the `jedec,spi-nor` interface to
access onboard flash memory. This ensures compatibility with common NOR
flash devices used in boot and storage subsystem.

Further improvements, including performance tuning and extended hardware
feature support, will be submitted in follow-up patches.
spi: axiado: Add driver for Axiado SPI DB controller 2026-01-09T13:21:55+00:00 Vladimir Moravcevic vmoravcevic@axiado.com 2026-01-08T07:44:38+00:00 e75a6b00ad7962a7ed1c9c777e9ab1eb29043ec8 The Axiado SPI controller is present in AX3000 SoC and Evaluation Board. This controller is operating in Host only mode. Co-developed-by: Prasad Bolisetty <pbolisetty@axiado.com> Signed-off-by: Prasad Bolisetty <pbolisetty@axiado.com> Signed-off-by: Vladimir Moravcevic <vmoravcevic@axiado.com> Link: https://patch.msgid.link/20260107-axiado-ax3000-soc-spi-db-controller-driver-v3-2-726e70cf19ad@axiado.com Signed-off-by: Mark Brown <broonie@kernel.org> 
The Axiado SPI controller is present in AX3000 SoC and Evaluation Board.
This controller is operating in Host only mode.

Co-developed-by: Prasad Bolisetty <pbolisetty@axiado.com>
Signed-off-by: Prasad Bolisetty <pbolisetty@axiado.com>
Signed-off-by: Vladimir Moravcevic <vmoravcevic@axiado.com>
Link: https://patch.msgid.link/20260107-axiado-ax3000-soc-spi-db-controller-driver-v3-2-726e70cf19ad@axiado.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: atcspi200: Add support for Andes ATCSPI200 SPI 2025-12-18T09:53:54+00:00 Mark Brown broonie@kernel.org 2025-12-18T09:53:54+00:00 65ccce35fa7a3b52713bd128fd211a80afc08abd Merge series from CL Wang <cl634@andestech.com>: This series adds support for the Andes ATCSPI200 SPI controller. 
Merge series from CL Wang <cl634@andestech.com>:

This series adds support for the Andes ATCSPI200 SPI controller.
spi: atcspi200: Add ATCSPI200 SPI controller driver 2025-12-17T12:04:53+00:00 CL Wang cl634@andestech.com 2025-12-15T13:23:48+00:00 34e3815ea4597131d4324a4aa243d2201e672005 Add driver for the Andes ATCSPI200 SPI controller. Signed-off-by: CL Wang <cl634@andestech.com> Link: https://patch.msgid.link/20251215132349.513843-3-cl634@andestech.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Add driver for the Andes ATCSPI200 SPI controller.

Signed-off-by: CL Wang <cl634@andestech.com>
Link: https://patch.msgid.link/20251215132349.513843-3-cl634@andestech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: add driver for NXP XSPI controller 2025-12-17T12:04:47+00:00 Haibo Chen haibo.chen@nxp.com 2025-12-16T03:20:14+00:00 29c8c00d9f9db5fb659b6f05f9e8964afc13f3e2 Add driver support for NXP XSPI controller. XSPI is a flexible SPI host controller which supports up to 2 external devices (2 CS). It support Single/Dual/Quad/Octal mode data transfer. The difference between XSPI and Flexspi: 1.the register layout is total different. 2.XSPI support multiple independent execution environments (EENVs) for HW virtualization with some limitations. Each EENV has its own interrupt and its own set of programming registers that exists in a specific offset range in the XSPI memory map. The main environment (EENV0) address space contains all of the registers for controlling EENV0 plus all of the general XSPI control and programming registers. The register mnemonics for the user environments (EENV1 to EENV4) have "_SUB_n" appended to the mnemonic for the corresponding main-environment register. Current driver based on EENV0, which means system already give EENV0 right to linux. This driver use SPI memory interface of the SPI framework to issue flash memory operations. Tested this driver with UBIFS and mtd_debug on NXP i.MX943 EVK board which has one spi nor MT35XU512ABA flash. Now this driver has the following key features: - Support up to OCT DDR mode - Support AHB read - Support IP read and IP write - Support two CS Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Link: https://patch.msgid.link/20251216-xspi-v7-2-282525220979@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Add driver support for NXP XSPI controller.

XSPI is a flexible SPI host controller which supports up to
2 external devices (2 CS). It support Single/Dual/Quad/Octal
mode data transfer.

The difference between XSPI and Flexspi:
1.the register layout is total different.
2.XSPI support multiple independent execution environments
(EENVs) for HW virtualization with some limitations. Each EENV
has its own interrupt and its own set of programming registers
that exists in a specific offset range in the XSPI memory map.
The main environment (EENV0) address space contains all of the
registers for controlling EENV0 plus all of the general XSPI
control and programming registers. The register mnemonics for
the user environments (EENV1 to EENV4) have "_SUB_n" appended
to the mnemonic for the corresponding main-environment register.

Current driver based on EENV0, which means system already give
EENV0 right to linux.

This driver use SPI memory interface of the SPI framework to
issue flash memory operations. Tested this driver with UBIFS
and mtd_debug on NXP i.MX943 EVK board which has one spi nor
MT35XU512ABA flash. Now this driver has the following key
features:
- Support up to OCT DDR mode
- Support AHB read
- Support IP read and IP write
- Support two CS

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://patch.msgid.link/20251216-xspi-v7-2-282525220979@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Merge tag 'spi-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 2025-12-04T19:24:24+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-12-04T19:24:24+00:00 fa5ef105618ae9b5aaa51b3f09e41d88d4514207 Pull spi updates from Mark Brown: "This release is almost entirely new drivers, with a couple of small changes in generic code. The biggest individual update is a rename of the existing Microchip driver and the addition of a new driver for the silicon SPI controller in their PolarFire SoCs. The overlap between the soft IP supported by the current driver and this new one is regrettably all in the IP and not in the register interface offered to software. - Add a time offset parameter for offloads, allowing them to be defined in relation to each other. This is useful for IIO type applcations where you trigger an operation then read the result after a delay. - Add a tracepoint for flash exec_ops, bringing the flash support more in line with the debuggability of vanilla SPI. - Support for Airoha EN7523, Arduino MCUs, Aspeed AST2700, Microchip PolarFire SPI controllers, NXP i.MX51 ECSPI target mode, Qualcomm IPQ5414 and IPQ5332, Renesas RZ/T2H, RZ/V2N and RZ/2NH and SpacemiT K1 QuadSPI. There's also a small set of ASoC cleanups that I mistakenly applied to the SPI tree and then put more stuff on top of before it was brought to my attention, sorry about that" * tag 'spi-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (80 commits) spi: microchip-core: Refactor FIFO read and write handlers spi: ch341: fix out-of-bounds memory access in ch341_transfer_one spi: microchip-core: Remove unneeded PM related macro spi: microchip-core: Use SPI_MODE_X_MASK spi: microchip-core: Utilise temporary variable for struct device spi: microchip-core: Replace dead code (-ENOMEM error message) spi: microchip-core: use min() instead of min_t() spi: dt-bindings: airoha: add compatible for EN7523 spi: airoha-snfi: en7523: workaround flash damaging if UART_TXD was short to GND spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support spi: microchip: Enable compile-testing for FPGA SPI controllers spi: Fix potential uninitialized variable in probe() spi: rzv2h-rspi: add support for RZ/T2H and RZ/N2H spi: dt-bindings: renesas,rzv2h-rspi: document RZ/T2H and RZ/N2H spi: rzv2h-rspi: add support for loopback mode spi: rzv2h-rspi: add support for variable transfer clock spi: rzv2h-rspi: add support for using PCLK for transfer clock spi: rzv2h-rspi: make transfer clock rate finding chip-specific spi: rzv2h-rspi: avoid recomputing transfer frequency ... 
Pull spi updates from Mark Brown:
 "This release is almost entirely new drivers, with a couple of small
  changes in generic code.

  The biggest individual update is a rename of the existing Microchip
  driver and the addition of a new driver for the silicon SPI controller
  in their PolarFire SoCs. The overlap between the soft IP supported by
  the current driver and this new one is regrettably all in the IP and
  not in the register interface offered to software.

   - Add a time offset parameter for offloads, allowing them to be
     defined in relation to each other. This is useful for IIO type
     applcations where you trigger an operation then read the result
     after a delay.

   - Add a tracepoint for flash exec_ops, bringing the flash support
     more in line with the debuggability of vanilla SPI.

   - Support for Airoha EN7523, Arduino MCUs, Aspeed AST2700, Microchip
     PolarFire SPI controllers, NXP i.MX51 ECSPI target mode, Qualcomm
     IPQ5414 and IPQ5332, Renesas RZ/T2H, RZ/V2N and RZ/2NH and SpacemiT
     K1 QuadSPI.

  There's also a small set of ASoC cleanups that I mistakenly applied to
  the SPI tree and then put more stuff on top of before it was brought
  to my attention, sorry about that"

* tag 'spi-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (80 commits)
  spi: microchip-core: Refactor FIFO read and write handlers
  spi: ch341: fix out-of-bounds memory access in ch341_transfer_one
  spi: microchip-core: Remove unneeded PM related macro
  spi: microchip-core: Use SPI_MODE_X_MASK
  spi: microchip-core: Utilise temporary variable for struct device
  spi: microchip-core: Replace dead code (-ENOMEM error message)
  spi: microchip-core: use min() instead of min_t()
  spi: dt-bindings: airoha: add compatible for EN7523
  spi: airoha-snfi: en7523: workaround flash damaging if UART_TXD was short to GND
  spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support
  spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support
  spi: microchip: Enable compile-testing for FPGA SPI controllers
  spi: Fix potential uninitialized variable in probe()
  spi: rzv2h-rspi: add support for RZ/T2H and RZ/N2H
  spi: dt-bindings: renesas,rzv2h-rspi: document RZ/T2H and RZ/N2H
  spi: rzv2h-rspi: add support for loopback mode
  spi: rzv2h-rspi: add support for variable transfer clock
  spi: rzv2h-rspi: add support for using PCLK for transfer clock
  spi: rzv2h-rspi: make transfer clock rate finding chip-specific
  spi: rzv2h-rspi: avoid recomputing transfer frequency
  ...
spi: tegra114: remove Kconfig dependency on TEGRA20_APB_DMA 2025-11-26T12:30:15+00:00 Francesco Lavra flavra@baylibre.com 2025-11-26T09:50:27+00:00 3dcf44ab56e1d3ca3532083c0d5390b758e45b45 This driver runs also on Tegra SoCs without a Tegra20 APB DMA controller (e.g. Tegra234). Remove the Kconfig dependency on TEGRA20_APB_DMA; in addition, amend the help text to reflect the fact that this driver works on SoCs different from Tegra114. Fixes: bb9667d8187b ("arm64: tegra: Add SPI device tree nodes for Tegra234") Signed-off-by: Francesco Lavra <flavra@baylibre.com> Link: https://patch.msgid.link/20251126095027.4102004-1-flavra@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org> 
This driver runs also on Tegra SoCs without a Tegra20 APB DMA controller
(e.g. Tegra234).
Remove the Kconfig dependency on TEGRA20_APB_DMA; in addition, amend the
help text to reflect the fact that this driver works on SoCs different from
Tegra114.

Fixes: bb9667d8187b ("arm64: tegra: Add SPI device tree nodes for Tegra234")
Signed-off-by: Francesco Lavra <flavra@baylibre.com>
Link: https://patch.msgid.link/20251126095027.4102004-1-flavra@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: microchip: Enable compile-testing for FPGA SPI controllers 2025-11-25T16:13:14+00:00 Geert Uytterhoeven geert+renesas@glider.be 2025-11-25T16:06:56+00:00 84b7344c05c5e48db4cf75cd3e91aef8d553d88e The Microchip FPGA SPI controller driver builds fine on other platforms. While at it, drop a superfluous empty line. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/6f96848b026f9a343b80d48179149b30c6b76d1d.1764086805.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org> 
The Microchip FPGA SPI controller driver builds fine on other platforms.

While at it, drop a superfluous empty line.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/6f96848b026f9a343b80d48179149b30c6b76d1d.1764086805.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>