linux-toradex.git/drivers/spi/spi-amd.c, branch v6.14-rc2

spi: amd: Fix -Wuninitialized in amd_spi_exec_mem_op()

2025-01-14T15:07:11+00:00

After commit e6204f39fe3a ("spi: amd: Drop redundant check"), clang warns (or
errors with CONFIG_WERROR=y):

  drivers/spi/spi-amd.c:695:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized]
    695 |         return ret;
        |                ^~~
  drivers/spi/spi-amd.c:673:9: note: initialize the variable 'ret' to silence this warning
    673 |         int ret;
        |                ^
        |                 = 0
  1 error generated.

ret is no longer set on anything other than the default switch path.
Replace ret with a direct return of 0 at the end of the function and
-EOPNOTSUPP in the default case to resolve the warning.

Fixes: e6204f39fe3a ("spi: amd: Drop redundant check")
Reported-by: kernel test robot 
Closes: https://lore.kernel.org/oe-kbuild-all/202501112315.ugYQ7Ce7-lkp@intel.com/
Signed-off-by: Nathan Chancellor 
Reviewed-by: Miguel Ojeda 
Reviewed-by: Miquel Raynal 
Link: https://patch.msgid.link/20250111-spi-amd-fix-uninitialized-ret-v1-1-c66ab9f6a23d@kernel.org
Signed-off-by: Mark Brown

spi: amd: Drop redundant check

2025-01-09T20:16:25+00:00

Both spi and spi-mem cores already take care of checking the minimum and
maximum speed for transfers depending on the controller
capabilities. There is no reason to repeat this check in controller
drivers.

Once this possible error condition removed from the function, it makes
no longer sense to return an int.

Signed-off-by: Miquel Raynal 
Link: https://patch.msgid.link/20241224-winbond-6-11-rc1-quad-support-v2-4-ad218dbc406f@bootlin.com
Signed-off-by: Mark Brown

spi: amd: Support per spi-mem operation frequency switches

2025-01-09T20:16:24+00:00

Every ->exec_op() call correctly configures the spi bus speed to the
maximum allowed frequency for the memory using the constant spi default
parameter. Since we can now have per-operation constraints, let's use
the value that comes from the spi-mem operation structure instead. In
case there is no specific limitation for this operation, the default spi
device value will be given anyway.

This controller however performed a frequency check, which is also
observed during the ->check_op() phase.

The per-operation frequency capability is thus advertised to the spi-mem
core.

Cc: Sanjay R Mehta 
Signed-off-by: Miquel Raynal 
Link: https://patch.msgid.link/20241224-winbond-6-11-rc1-quad-support-v2-3-ad218dbc406f@bootlin.com
Signed-off-by: Mark Brown

spi: spi_amd: Add HIDDMA basic read support

2024-09-29T23:11:56+00:00

SPI index mode has hardware limitation of reading only 64 bytes per
transaction due to fixed number of FIFO registers. This constraint leads
to performance issues when reading data from NAND/NOR flash devices, as the
controller must issue multiple requests to read 64-byte chunks, even if the
slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI
controller supports DMA mode, which allows reading up to 4 KB of data in
single transaction. This patch introduces changes to implement HID2 DMA
read support for the HID2 SPI controller.

Co-developed-by: Krishnamoorthi M 
Signed-off-by: Krishnamoorthi M 
Co-developed-by: Akshata MukundShetty 
Signed-off-by: Akshata MukundShetty 
Signed-off-by: Raju Rangoju 
Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown

spi: spi_amd: Set controller address mode

2024-09-29T23:11:55+00:00

Add changes to set the controller address mode before initiating commands.
The AMD SPI0 controller(AMDI0062) supports both 24-bit and 32-bit address
modes, while the HID2 SPI controller(AMDI0063) supports only the 24-bit
address mode. So this change is applicable only for SPI0 controller.

Co-developed-by: Krishnamoorthi M 
Signed-off-by: Krishnamoorthi M 
Co-developed-by: Akshata MukundShetty 
Signed-off-by: Akshata MukundShetty 
Signed-off-by: Raju Rangoju 
Link: https://patch.msgid.link/20240925133644.2922359-8-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown

spi: spi_amd: Add support for HID2 SPI controller

2024-09-29T23:11:54+00:00

AMD SoC has HID2 SPI controller in addition to the existing SPI0
controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its
version ID to the list of supported devices. Use the version ID to
differentiate the register offsets.

And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB
of data to be read in single transaction. Update the SPI-MEM support
function to reflect this capability.

Co-developed-by: Krishnamoorthi M 
Signed-off-by: Krishnamoorthi M 
Co-developed-by: Akshata MukundShetty 
Signed-off-by: Akshata MukundShetty 
Signed-off-by: Raju Rangoju 
Link: https://patch.msgid.link/20240925133644.2922359-7-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown

spi: spi_amd: Optimize IO operations

2024-09-29T23:11:54+00:00

Read and write the maximum number of data bytes at once, rather than byte
by byte. This improves AMD SPI controller driver performance by reducing
the time required to access FIFO registers. For example, with the new
changes, 64 bytes of data from the FIFO queue can be read in 8 read calls
(8 bytes per call) instead of 64 read calls(1 byte per call).

Co-developed-by: Krishnamoorthi M 
Signed-off-by: Krishnamoorthi M 
Co-developed-by: Akshata MukundShetty 
Signed-off-by: Akshata MukundShetty 
Signed-off-by: Raju Rangoju 
Link: https://patch.msgid.link/20240925133644.2922359-6-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown

spi: spi_amd: Updates to set tx/rx count functions

2024-09-29T23:11:53+00:00

AMD SPI TX and RX counter registers are 1-byte length registers. The
existing value will be overwritten during register write, so masking is not
required.

Co-developed-by: Krishnamoorthi M 
Signed-off-by: Krishnamoorthi M 
Co-developed-by: Akshata MukundShetty 
Signed-off-by: Akshata MukundShetty 
Signed-off-by: Raju Rangoju 
Link: https://patch.msgid.link/20240925133644.2922359-5-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown

spi: spi_amd: Replace ioread/iowrite calls

2024-09-29T23:11:52+00:00

All `ioread*` and `iowrite*` functions are better suited for architecture
independent code to ensure portability across different architectures.
Since AMD SoCs support only the x86 architecture, replacing all `ioread*`
and `iowrite*` calls with `read*` and `write*` calls can reduce the
overhead of ensuring portability and increase the speed of I/O operations.

Co-developed-by: Krishnamoorthi M 
Signed-off-by: Krishnamoorthi M 
Co-developed-by: Akshata MukundShetty 
Signed-off-by: Akshata MukundShetty 
Signed-off-by: Raju Rangoju 
Link: https://patch.msgid.link/20240925133644.2922359-4-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown

spi: spi_amd: Enable dual and quad I/O modes

2024-09-29T23:11:51+00:00

The current spi_amd driver only supports single I/O mode, despite the AMD
SPI controller's capability for dual and quad I/O modes for read
operations. And AMD SPI0 controller has limited support for quad mode
write operations. Update the SPI-MEM support function to reflect these
hardware capabilities.

Co-developed-by: Krishnamoorthi M 
Signed-off-by: Krishnamoorthi M 
Co-developed-by: Akshata MukundShetty 
Signed-off-by: Akshata MukundShetty 
Signed-off-by: Raju Rangoju 
Link: https://patch.msgid.link/20240925133644.2922359-3-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown