linux-toradex.git/drivers/spi/spi-intel.c, branch v6.10-rc2

spi: intel: Keep the BIOS partition inside the first chip

2024-02-05T14:35:47+00:00

If there are two flash chips connected flash regions can refer to the
second chip too. In this case we may see the following warning:

  mtd: partition "BIOS" extends beyond the end of device "0000:00:1f.5" --
  	size truncated to 0x400000

For this reason, check the BIOS partition size against the chip size and
make sure it stays within the that.

Signed-off-by: Mika Westerberg 
Link: https://lore.kernel.org/r/20240201121638.207632-2-mika.westerberg@linux.intel.com
Signed-off-by: Mark Brown

spi: intel: Add default partition and name to the second chip

2024-02-05T14:35:46+00:00

This should make it easier to identify the second chip and also allows
using "mtdparts=" and the like with this chip too.

Signed-off-by: Mika Westerberg 
Link: https://lore.kernel.org/r/20240201121638.207632-1-mika.westerberg@linux.intel.com
Signed-off-by: Mark Brown

spi: intel: make mem_ops comparison unique to opcode match

2023-11-18T12:36:34+00:00

Instead of comparing parameters for every supported mem_ops, only compare
on opcode match, which is relatively more efficient.

Signed-off-by: Raag Jadav 
Reviewed-by: Mika Westerberg 
Link: https://lore.kernel.org/r/20231117144053.24005-1-raag.jadav@intel.com
Signed-off-by: Mark Brown

spi: intel: switch to use modern name

2023-08-14T12:11:04+00:00

Change legacy name master to modern name host or controller.

No functional changed.

Signed-off-by: Yang Yingliang 
Link: https://lore.kernel.org/r/20230807124105.3429709-19-yangyingliang@huawei.com
Signed-off-by: Mark Brown

spi: Replace all spi->chip_select and spi->cs_gpiod references with function call

2023-03-11T12:34:01+00:00

Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod
members of struct spi_device to be an array. But changing the type of these
members to array would break the spi driver functionality. To make the
transition smoother introduced four new APIs to get/set the
spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and
spi->cs_gpiod references with get or set API calls.
While adding multi-cs support in further patches the chip_select & cs_gpiod
members of the spi_device structure would be converted to arrays & the
"idx" parameter of the APIs would be used as array index i.e.,
spi->chip_select[idx] & spi->cs_gpiod[idx] respectively.

Signed-off-by: Amit Kumar Mahapatra 
Acked-by: Heiko Stuebner  # Rockchip drivers
Reviewed-by: Michal Simek 
Reviewed-by: Cédric Le Goater  # Aspeed driver
Reviewed-by: Dhruva Gole  # SPI Cadence QSPI
Reviewed-by: Patrice Chotard  # spi-stm32-qspi
Acked-by: William Zhang  # bcm63xx-hsspi driver
Reviewed-by: Serge Semin  # DW SSI part
Link: https://lore.kernel.org/r/167847070432.26.15076794204368669839@mailman-core.alsa-project.org
Signed-off-by: Mark Brown

Merge remote-tracking branch 'spi/for-6.3' into spi-next

2023-02-17T22:05:55+00:00

spi: intel: Check number of chip selects after reading the descriptor

2023-02-15T13:10:42+00:00

The flash decriptor contains the number of flash components that we use
to figure out how many flash chips there are connected. Therefore we
need to read it first before deciding how many chip selects the
controller has.

Reported-by: Marcin Witkowski 
Fixes: 3f03c618bebb ("spi: intel: Add support for second flash chip")
Cc: stable@vger.kernel.org
Signed-off-by: Mika Westerberg 
Link: https://lore.kernel.org/r/20230215110040.42186-1-mika.westerberg@linux.intel.com
Signed-off-by: Mark Brown

spi: intel: Fix device private data and PR_NUM for Broxton controllers

2023-02-02T11:42:29+00:00

Some private data fields have to change from bxt_info to cnl_info.
Here is the list of Device IDs with the respective documentation taken for
validation:
    0xa0a4 - Intel® 500 Series Chipset Family On-Package PCH
    0x02a4 - Intel® 400 Series Chipset Family On-Package PCH
    0x06a4 - Intel® 400 Series Chipset Family Platform Controller Hub
    0x34a4 - Intel® 495 Chipset Family On-Package
    0xa3a4 - Intel® B460 and H410 Chipset

According to documentation Broxton controller type has five PR registers.

Signed-off-by: Mauro Lima 
Acked-by: Mika Westerberg 
Link: https://lore.kernel.org/r/20230201205455.550308-2-mauro.lima@eclypsium.com
Signed-off-by: Mark Brown

Merge tag 'spi-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

2022-12-13T20:54:31+00:00

Pull spi updates from Mark Brown:
 "A busy enough release, but not for the core which has only seen very
  small updates. The biggest addition is the readdition of support for
  detailed configuration of the timings around chip selects. That had
  been removed for lack of use but there's been applications found for
  it on Atmel systems. Otherwise the updates are mostly feature
  additions and cleanups to existing drivers.

  Summary:

   - Provide a helper for getting device match data in a way that
     abstracts away which firmware interface is being used.

   - Re-add the spi_set_cs_timing() API for detailed configuration of
     the timing around chip select and support it on Atmel.

   - Support for MediaTek MT7986, Microchip PCI1xxxx, Nuvoton WPCM450
     FIU and Socionext F_OSPI"

* tag 'spi-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (66 commits)
  spi: dt-bindings: Convert Synquacer SPI to DT schema
  spi: spi-gpio: Don't set MOSI as an input if not 3WIRE mode
  spi: spi-mtk-nor: Add recovery mechanism for dma read timeout
  spi: spi-fsl-lpspi: add num-cs binding for lpspi
  spi: spi-fsl-lpspi: support multiple cs for lpspi
  spi: mtk-snfi: Add snfi support for MT7986 IC
  spi: spidev: mask SPI_CS_HIGH in SPI_IOC_RD_MODE
  spi: cadence-quadspi: Add minimum operable clock rate warning to baudrate divisor calculation
  spi: microchip: pci1xxxx: Add suspend and resume support for PCI1XXXX SPI driver
  spi: dt-bindings: nuvoton,wpcm450-fiu: Fix warning in example (missing reg property)
  spi: dt-bindings: nuvoton,wpcm450-fiu: Fix error in example (bogus include)
  spi: mediatek: Enable irq when pdata is ready
  spi: spi-mtk-nor: Unify write buffer on/off
  spi: intel: Add support for SFDP opcode
  spi: intel: Take possible chip address into account in intel_spi_read/write_reg()
  spi: intel: Implement adjust_op_size()
  spi: intel: Use ->replacement_op in intel_spi_hw_cycle()
  spi: cadence: Drop obsolete dependency on COMPILE_TEST
  spi: Add Nuvoton WPCM450 Flash Interface Unit (FIU) bindings
  spi: wpcm-fiu: Add direct map support
  ...

spi: intel: Add support for SFDP opcode

2022-11-25T19:34:06+00:00

The Intel SPI-NOR controller supports SFDP (Serial Flash Discoverable
Parameter) opcode so add it to the list of supported opcodes.

Signed-off-by: Mika Westerberg 
Link: https://lore.kernel.org/r/20221025064623.22808-5-mika.westerberg@linux.intel.com
Signed-off-by: Mark Brown