Merge series from Andy Shevchenko <andriy.shevchenko@linux.intel.com>: Recently in the discussion with David the idea of having a common helper popped up. The helper converts the given bits per word to bytes. The result will always be power-of-two (e.g. for 37 bits it returns 8 bytes) or 0 for 0 input. More details are in the respective code comment. This mini-series introduces it and replaces current users under drivers/spi and we expect more (and possibly some lurking in other subsystems).
This helper converts the given bits per word to bytes. The result
will always be power-of-two, e.g.,
=============== =================
Input (in bits) Output (in bytes)
=============== =================
5 1
9 2
21 4
37 8
=============== =================
It will return 0 for the 0 input.
There are a couple of cases in SPI that are using the same approach
and at least one more (in IIO) would benefit of it. Add a helper
for everyone.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20250417152529.490582-2-andriy.shevchenko@linux.intel.com
Acked-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Introduce support for protocol drivers to specify whether a transfer should use single or dual transfer mode. Currently, the SPI controller cannot determine this information from the user, leading to potential limitations in transfer capabilities. Add a new field `dtr_mode` in the `spi_transfer` structure. The `dtr_mode` field allows protocol drivers to indicate if Double Transfer Rate (DTR) mode is supported for a given transfer. When `dtr_mode` is set to true, the SPI controller will use DTR mode; otherwise, it will default to single transfer mode. Introduce another field `dtr_caps` to indicate if the QSPI controller is capable of supporting DTR mode (SDR and DDR). By default, both `dtr_caps` and `dtr_mode` will be false. These flags manage the QSPI controller's DTR mode capabilities within the SPI framework. The QSPI controller driver uses these flags to configure single or double transfer rates using the controller register. The existing spi-mem driver helps configure the DTR mode but is limited to memory devices. There is no support available to set DTR mode for non-memory devices, e.g., touch or any generic SPI sensor. This change is backward compatible and doesn't break existing SPI or QSPI drivers. Changes include: - Addition of `dtr_mode` and `dtr_caps` fields in the `spi_transfer` structure. - Documentation updates to reflect the new `dtr_mode` and `dtr_caps` fields. Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> Link: https://patch.msgid.link/20250404135427.313825-1-quic_msavaliy@quicinc.com Signed-off-by: Mark Brown <broonie@kernel.org>
First of all, the (foo && bar) || (!foo && !bar) when foo and bar are booleans is equivalent to (foo == bar). Second, reuse variable that holds already the calculation of the SPI CS mode to be active-high. No functional changes intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20250331093915.4041600-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
Pull spi updates from Mark Brown:
"The biggest change for SPI this release is the addition of offload
support from David Lechner, allowing the hardware to trigger SPI
transactions autonomously. The initial use case is for triggering IIO
operations but there are other applications where having the hardware
ready to go at a minimal signal is useful for synchronising with
external inputs (eg, interrupt handling) or reducing latency (eg, CAN
networking).
Otherwise there's the usual fixes, improvements and cleanups, plus
support for a bunch of new devices.
- Support for offloading support from David Lechner
- Support for GOcontrol1 Moduline modules, Mediatek MT7988, NXP
i.MX94, Qualcomm SPI NAMD, Rockchip RK3562, Sophogo SG2044 and ST
STM32 OSPI"
* tag 'spi-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (59 commits)
spi: spi-mem: Introduce a default ->exec_op() debug log
spi: dt-bindings: cdns,qspi-nor: Require some peripheral properties
spi: dt-bindings: cdns,qspi-nor: Deprecate the Cadence compatible alone
spi: dt-bindings: cdns,qspi-nor: Be more descriptive regarding what this controller is
spi: stm32-ospi: Include "gpio/consumer.h"
MAINTAINERS: adjust the file entry in GOCONTROLL MODULINE MODULE SLOT
spi: spi-qpic-snand: avoid memleak in qcom_spi_ecc_init_ctx_pipelined()
spi: spi-mux: Fix coverity issue, unchecked return value
spi: sophgo: fix incorrect type for ret in sg2044_spifmc_write()
spi: sg2044-nor: fix uninitialized variable in probe
spi: sg2044-nor: fix signedness bug in sg2044_spifmc_write()
spi: sg2044-nor: Convert to dev_err_probe()
spi: sg2044-nor: Fully convert to device managed resources
dt-bindings: spi: add compatibles for mt7988
spi: spidev: Add an entry for the gocontroll moduline module slot
MAINTAINERS: add maintainer for the GOcontroll Moduline module slot
dt-bindings: connector: Add the GOcontroll Moduline module slot bindings
dt-bindings: vendor-prefixes: add GOcontroll
spi: Use inclusive language
spi: cadence-qspi: Improve spi memory performance
...
Fix a reference count leak in slave_show() by properly putting the device
reference obtained from device_find_any_child().
Fixes: 6c364062bfed ("spi: core: Add support for registering SPI slave controllers")
Fixes: c21b0837983d ("spi: Use device_find_any_child() instead of custom approach")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250319032305.70340-1-linmq006@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Replace "master" by "[host] controller" in the SPI core code and comments. All the similar to the "slave" by "target [device]" changes. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20250313140340.380359-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
Merge series from David Lechner <dlechner@baylibre.com>: As a recap, here is the background and end goal of this series: The AXI SPI Engine is a SPI controller that has the ability to record a series of SPI transactions and then play them back using a hardware trigger. This allows operations to be performed, repeating many times, without any CPU intervention. This is needed for achieving high data rates (millions of samples per second) from ADCs and DACs that are connected via a SPI bus. The offload hardware interface consists of a trigger input and a data output for the RX data. These are connected to other hardware external to the SPI controller. To record one or more transactions, commands and TX data are written to memories in the controller (RX buffer is not used since RX data gets streamed to an external sink). This sequence of transactions can then be played back when the trigger input is asserted. This series includes core SPI support along with the first SPI controller (AXI SPI Engine) and SPI peripheral (AD7944 ADC) that use them. This enables capturing analog data at 2 million samples per second. The hardware setup looks like this: +-------------------------------+ +------------------+ | | | | | SOC/FPGA | | AD7944 ADC | | +---------------------+ | | | | | AXI SPI Engine | | | | | | SPI Bus ============ SPI Bus | | | | | | | | | +---------------+ | | | | | | | Offload 0 | | | +------------------+ | | | RX DATA OUT > > > > | | | | TRIGGER IN < < < v | | | +---------------+ | ^ v | | +---------------------+ ^ v | | | AXI PWM | ^ v | | | CH0 > ^ v | | +---------------------+ v | | | AXI DMA | v | | | CH0 < < < | | +---------------------+ | | | +-------------------------------+
Most configuration of SPI offloads is handled opaquely using the offload pointer that is passed to the various offload functions. However, there are some offload features that need to be controlled on a per transfer basis. This patch adds a flag field to struct spi_transfer to allow specifying such features. The first feature to be added is the ability to stream data to/from a hardware sink/source rather than using a tx or rx buffer. Additional flags can be added in the future as needed. A flags field is also added to the offload struct for providers to indicate which flags are supported. This allows for generic checking of offload capabilities during __spi_validate() so that each offload provider doesn't have to implement their own validation. As a first users of this streaming capability, getter functions are added to get a DMA channel that is directly connected to the offload. Peripheral drivers will use this to get a DMA channel and configure it to suit their needs. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Nuno Sa <nuno.sa@analog.com> Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250207-dlech-mainline-spi-engine-offload-2-v8-5-e48a489be48c@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
_spi_transfer_delay_ns() partially reimplements what fsleep() does. Replace that code by calling fsleep() instead. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20250205130624.716039-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>