linux-toradex.git/drivers/spi, branch v2.6.25-rc7

spi_bitbang: short transfer status fix

2008-03-13T20:11:43+00:00

SPI controller drivers return number of bytes actually transfered from
bitbang->txrx_bufs() method.  This updates handling of short transfers (where
the transfer size is less than requested):

 - Even zero byte short transfers should report errors;
 - Include short transfers in the total of transferred bytes;
 - Use EREMOTEIO (like USB) not EMSGSIZE to report short transfers

Short transfers don't normally mean invalid message sizes, but if the
underlying controller driver needs to use EMSGSIZE it can still do so.

[db: fix two more minor issues]
Signed-off-by: Jan Nikitenko 
Signed-off-by: David Brownell 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

au1550_spi: fix prototype of irq handler

2008-03-13T20:11:43+00:00

Remove struct pt_regs *regs from prototype of au1550_spi_irq handler to avoid
warning in request_irq().  Also fix comment type leadin.

Signed-off-by: Jan Nikitenko 
Signed-off-by: David Brownell 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

powerpc: mpc5200: fix build error on mpc52xx_psc_spi device driver

2008-03-05T00:35:12+00:00

Commit id 94f389485e27641348c1951ab8d65157122a8939 (Separate MPC52xx PSC FIOF
regsiters from the rest of PSC) split the PSC fifo registers away from the
core PSC regs.  Doing so broke the mpc52xx_psc_spi driver.

This patch teaches the mpc52xx_psc_spi driver about the new PSC fifo
register definitions.

Signed-off-by: Grant Likely 
Cc: David Brownell 
Cc: Paul Mackerras 
Cc: Benjamin Herrenschmidt 
Cc: Kumar Gala 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

spi: pxa2xx_spi clock polarity fix

2008-02-24T01:12:14+00:00

Fixes a sequencing bug in spi driver pxa2xx_spi.c in which the chip select
for a transfer may be asserted before the clock polarity is set on the
interface.  As a result of this bug, the clock signal may have the wrong
polarity at transfer start, so it may need to make an extra half transition
before the intended clock/data signals begin.  (This probably means all
transfers are one bit out of sequence.)

This only occurs on the first transfer following a change in clock polarity
in systems using more than one more than one such polarity.  The fix
assures that the clock mode is properly set before asserting chip select.

This bug was introduced in a patch merged on 2006/12/10, kernel 2.6.20.
The patch defines an additional bit in: include/asm-arm/arch-pxa/regs-ssp.h
for 2.6.25 and newer kernels but this addition must be made in:
include/asm-arm/arch-pxa/pxa-regs.h for kernels between 2.6.20 and 2.6.24,
inclusive

Signed-off-by: Ned Forrester 
Signed-off-by: David Brownell 
Cc: Russell King 
Cc: 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

atmel_spi: fix clock polarity

2008-02-24T01:12:14+00:00

The atmel_spi driver does not initialize clock polarity correctly (except for
at91rm9200 CS0 channel) in some case.

The atmel_spi driver uses gpio-controlled chipselect.  OTOH spi clock signal
is controlled by CSRn.CPOL bit, but this register controls clock signal
correctly only in 'real transfer' duration.  At the time of cs_activate()
call, CSRn.CPOL will be initialized correctly, but the controller do not know
which channel is to be used next, so clock signal will stay at the inactive
state of last transfer.  If clock polarity of new transfer and last transfer
was differ, new transfer will start with wrong clock signal state.

For example, if you started SPI MODE 2 or 3 transfer after SPI MODE 0 or 1
transfer, the clock signal state at the assertion of chipselect will be low.
Of course this will violates SPI transfer.

This patch is short term solution for this problem.  It makes all CSRn.CPOL
match for the transfer before activating chipselect.  For longer term, the
best fix might be to let NPCS0 stay selected permanently in MR and overwrite
CSR0 with to the new slave's settings before asserting CS.

Signed-off-by: Atsushi Nemoto 
Acked-by: Haavard Skinnemoen 
Cc: David Brownell 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

spi: remove more dev->power.power_state usage

2008-02-06T18:41:11+00:00

Remove some more references to dev->power.power_state.  That field is overdue
for removal, but we can't do that while it's still referenced in the kernel.
The only reason to update it was to make the /sys/devices/.../power/state
files (now removed) work better.

Signed-off-by: David Brownell 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

spi_bfin: headers are not for changelogs

2008-02-06T18:41:11+00:00

Use simpler comment headers, and strip out information that is maintained in
GIT history

Signed-off-by: Mike Frysinger 
Signed-off-by: Bryan Wu 
Signed-off-by: David Brownell 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

spi_bfin: wait for tx to complete on write paths

2008-02-06T18:41:11+00:00

SPI writes should also not return until the last bit is sent.

Signed-off-by: Sonic Zhang 
Signed-off-by: Bryan Wu 
Signed-off-by: David Brownell 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

spi_bfin: wait for tx to complete on full duplex paths

2008-02-06T18:41:11+00:00

Full duplex SPI operation should not read a dummy byte at the first transfer.
Bug and fix by Jean-Christian de Rivaz :

http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3678

Signed-off-by: Jean-Christian de Rivaz 
Signed-off-by: Bryan Wu 
Signed-off-by: David Brownell 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

spi_bfin: wait for tx to complete on some cs_chg paths

2008-02-06T18:41:11+00:00

PBX 2 SPI devices need the nonstandard "cs change per word" mechanism.

This patch is one of three updating this driver to make the last data bits get
sent before advancing the transfer ...  in this case, before the chipselect
gets deactivated.

Signed-off-by: Bryan Wu 
Signed-off-by: David Brownell 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds