linux-toradex.git/drivers/tty/serial/8250, branch v3.13.9

serial: 8250: enable UART_BUG_NOMSR for Tegra

2014-02-06T19:34:00+00:00

commit 3685f19e07802ec4207b52465c408f185b66490e upstream.

Tegra chips have 4 or 5 identical UART modules embedded. UARTs C..E have
their MODEM-control signals tied off to a static state. However UARTs A
and B can optionally route those signals to/from package pins, depending
on the exact pinmux configuration.

When these signals are not routed to package pins, false interrupts may
trigger either temporarily, or permanently, all while not showing up in
the IIR; it will read as NO_INT. This will eventually lead to the UART
IRQ being disabled due to unhandled interrupts. When this happens, the
kernel may print e.g.:

    irq 68: nobody cared (try booting with the "irqpoll" option)

In order to prevent this, enable UART_BUG_NOMSR. This prevents
UART_IER_MSI from being enabled, which prevents the false interrupts
from triggering.

In practice, this is not needed under any of the following conditions:

* On Tegra chips after Tegra30, since the HW bug has apparently been
  fixed.

* On UARTs C..E since their MODEM control signals are tied to the correct
  static state which doesn't trigger the issue.

* On UARTs A..B if the MODEM control signals are routed out to package
  pins, since they will then carry valid signals.

However, we ignore these exceptions for now, since they are only relevant
if a board actually hooks up more than a 4-wire UART, and no currently
supported board does this. If we ever support a board that does, we can
refine the algorithm that enables UART_BUG_NOMSR to take those exceptions
into account, and/or read a flag from DT/... that indicates that the
board has hooked up and pinmux'd more than a 4-wire UART.

Reported-by: Olof Johansson  # autotester
Signed-off-by: Stephen Warren 
Signed-off-by: Greg Kroah-Hartman

serial: 8250: Fix initialisation of Quatech cards with the AMCC PCI chip

2014-02-06T19:34:00+00:00

commit 9c5320f8d7d9a2cf623e65d50e1113f34d9b9eb1 upstream.

Fix the initialisation of older Quatech serial cards which are fitted with
the AMCC PCI Matchmaker interface chip.

Signed-off-by: Jonathan Woithe (jwoithe@just42.net)
Signed-off-by: Greg Kroah-Hartman

serial: add support for 200 v3 series Titan card

2014-02-06T19:34:00+00:00

commit 48c0247d7b7bf58abb85a39021099529df365c4d upstream.

Signed-off-by: Yegor Yefremov 
Signed-off-by: Greg Kroah-Hartman

serial: 8250_dw: add new ACPI IDs

2013-12-17T17:41:45+00:00

Newer Intel PCHs with LPSS have the same Designware controllers than
Haswell but ACPI IDs are different. Add these IDs to the driver list.

Signed-off-by: Mika Westerberg 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman

serial: 8250_dw: Fix LCR workaround regression

2013-12-17T01:10:46+00:00

Commit c49436b657d0 (serial: 8250_dw: Improve unwritable LCR workaround)
caused a regression. It added a check that the LCR was written properly
to detect and workaround the busy quirk, but the behaviour of bit 5
(UART_LCR_SPAR) differs between IP versions 3.00a and 3.14c per the
docs. On older versions this caused the check to fail and it would
repeatedly force idle and rewrite the LCR register, causing delays and
preventing any input from serial being received.

This is fixed by masking out UART_LCR_SPAR before making the comparison.

Signed-off-by: James Hogan 
Cc: Greg Kroah-Hartman 
Cc: Jiri Slaby 
Cc: Tim Kryger 
Cc: Ezequiel Garcia 
Cc: Matt Porter 
Cc: Markus Mayer 
Tested-by: Tim Kryger 
Tested-by: Ezequiel Garcia 
Tested-by: Heikki Krogerus 
Signed-off-by: Greg Kroah-Hartman

tty/serial/8250: fix typo in help text

2013-11-25T16:52:53+00:00

Commit 9326b047e4fd4a8da72e59d913214a1803e9709c includes a typo
of "8350_core" instead of "8250_core", so correct it.

Fixes kernel bugzilla #60724:
  https://bugzilla.kernel.org/show_bug.cgi?id=60724

Reported-by: Christoph Biedl 
Signed-off-by: Randy Dunlap 
Cc: Jiri Slaby 
Signed-off-by: Greg Kroah-Hartman

serial: 8250_pci: add Pericom PCIe Serial board Support (12d8:7952/4/8) - Chip PI7C9X7952/4/8

2013-10-20T02:51:17+00:00

Signed-off-by: Angelo Butti 
Signed-off-by: Greg Kroah-Hartman

serial: 8250_pci: add support for Fintek 4, 8, and 12 port cards

2013-10-17T20:21:59+00:00

This adds support for Fintek's 4, 8, and 12 port PCIE serial cards.

Thanks to Fintek for the sample devices, and the spec needed in order to
implement this.

Cc: Amanda Ying 
Cc: Felix Shih 
Signed-off-by: Greg Kroah-Hartman

serial8250-em: convert to clk_prepare/unprepare

2013-10-16T20:07:14+00:00

Add calls to clk_prepare and unprepare so that EMMA Mobile EV2 can
migrate to the common clock framework.

Signed-off-by: Shinya Kuribayashi 
[takashi.yoshii.ze@renesas.com: edited for conflicts]
Signed-off-by: Takashi Yoshii 
Acked-by: Greg Kroah-Hartman 
Acked-by: Laurent Pinchart 
Acked-by: Magnus Damm 
Signed-off-by: Simon Horman 
Signed-off-by: Greg Kroah-Hartman

serial: 8250_dw: Improve unwritable LCR workaround

2013-10-03T23:08:03+00:00

When configured with UART_16550_COMPATIBLE=NO or in versions prior to
the introduction of this option, the Designware UART will ignore writes
to the LCR if the UART is busy.  The current workaround saves a copy of
the last written LCR and re-writes it in the ISR for a special interrupt
that is raised when a write was ignored.

Unfortunately, interrupts are typically disabled prior to performing a
sequence of register writes that include the LCR so the point at which
the retry occurs is too late.  An example is serial8250_do_set_termios()
where an ignored LCR write results in the baud divisor not being set and
instead a garbage character is sent out the transmitter.

Furthermore, since serial_port_out() offers no way to indicate failure,
a serious effort must be made to ensure that the LCR is actually updated
before returning back to the caller.  This is difficult, however, as a
UART that was busy during the first attempt is likely to still be busy
when a subsequent attempt is made unless some extra action is taken.

This updated workaround reads back the LCR after each write to confirm
that the new value was accepted by the hardware.  Should the hardware
ignore a write, the TX/RX FIFOs are cleared and the receive buffer read
before attempting to rewrite the LCR out of the hope that doing so will
force the UART into an idle state.  While this may seem unnecessarily
aggressive, writes to the LCR are used to change the baud rate, parity,
stop bit, or data length so the data that may be lost is likely not
important.  Admittedly, this is far from ideal but it seems to be the
best that can be done given the hardware limitations.

Lastly, the revised workaround doesn't touch the LCR in the ISR, so it
avoids the possibility of a "serial8250: too much work for irq" lock up.
This problem is rare in real situations but can be reproduced easily by
wiring up two UARTs and running the following commands.

  # stty -F /dev/ttyS1 echo
  # stty -F /dev/ttyS2 echo
  # cat /dev/ttyS1 &
  [1] 375
  # echo asdf > /dev/ttyS1
  asdf

  [   27.700000] serial8250: too much work for irq96
  [   27.700000] serial8250: too much work for irq96
  [   27.710000] serial8250: too much work for irq96
  [   27.710000] serial8250: too much work for irq96
  [   27.720000] serial8250: too much work for irq96
  [   27.720000] serial8250: too much work for irq96
  [   27.730000] serial8250: too much work for irq96
  [   27.730000] serial8250: too much work for irq96
  [   27.740000] serial8250: too much work for irq96

Signed-off-by: Tim Kryger 
Reviewed-by: Matt Porter 
Reviewed-by: Markus Mayer 
Reviewed-by: Heikki Krogerus 
Signed-off-by: Greg Kroah-Hartman