linux-toradex.git/drivers/ufs/host, branch v6.10 Linux kernel for Apalis and Colibri modules Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi 2024-05-15T01:25:53+00:00 Linus Torvalds torvalds@linux-foundation.org 2024-05-15T01:25:53+00:00 113d1dd9c8ea2186d56a641a787e2588673c9c32 Pull SCSI updates from James Bottomley: "Updates to the usual drivers (ufs, lpfc, qla2xxx, mpi3mr, libsas). The major update (which causes a conflict with block, see below) is Christoph removing the queue limits and their associated block helpers. The remaining patches are assorted minor fixes and deprecated function updates plus a bit of constification" * tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (141 commits) scsi: mpi3mr: Sanitise num_phys scsi: lpfc: Copyright updates for 14.4.0.2 patches scsi: lpfc: Update lpfc version to 14.4.0.2 scsi: lpfc: Add support for 32 byte CDBs scsi: lpfc: Change lpfc_hba hba_flag member into a bitmask scsi: lpfc: Introduce rrq_list_lock to protect active_rrq_list scsi: lpfc: Clear deferred RSCN processing flag when driver is unloading scsi: lpfc: Update logging of protection type for T10 DIF I/O scsi: lpfc: Change default logging level for unsolicited CT MIB commands scsi: target: Remove unused list 'device_list' scsi: iscsi: Remove unused list 'connlist_err' scsi: ufs: exynos: Add support for Tensor gs101 SoC scsi: ufs: exynos: Add some pa_dbg_ register offsets into drvdata scsi: ufs: exynos: Allow max frequencies up to 267Mhz scsi: ufs: exynos: Add EXYNOS_UFS_OPT_TIMER_TICK_SELECT option scsi: ufs: exynos: Add EXYNOS_UFS_OPT_UFSPR_SECURE option scsi: ufs: dt-bindings: exynos: Add gs101 compatible scsi: qla2xxx: Fix debugfs output for fw_resource_count scsi: qedf: Ensure the copied buf is NUL terminated scsi: bfa: Ensure the copied buf is NUL terminated ... 
Pull SCSI updates from James Bottomley:
 "Updates to the usual drivers (ufs, lpfc, qla2xxx, mpi3mr, libsas).

  The major update (which causes a conflict with block, see below) is
  Christoph removing the queue limits and their associated block
  helpers.

  The remaining patches are assorted minor fixes and deprecated function
  updates plus a bit of constification"

* tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (141 commits)
  scsi: mpi3mr: Sanitise num_phys
  scsi: lpfc: Copyright updates for 14.4.0.2 patches
  scsi: lpfc: Update lpfc version to 14.4.0.2
  scsi: lpfc: Add support for 32 byte CDBs
  scsi: lpfc: Change lpfc_hba hba_flag member into a bitmask
  scsi: lpfc: Introduce rrq_list_lock to protect active_rrq_list
  scsi: lpfc: Clear deferred RSCN processing flag when driver is unloading
  scsi: lpfc: Update logging of protection type for T10 DIF I/O
  scsi: lpfc: Change default logging level for unsolicited CT MIB commands
  scsi: target: Remove unused list 'device_list'
  scsi: iscsi: Remove unused list 'connlist_err'
  scsi: ufs: exynos: Add support for Tensor gs101 SoC
  scsi: ufs: exynos: Add some pa_dbg_ register offsets into drvdata
  scsi: ufs: exynos: Allow max frequencies up to 267Mhz
  scsi: ufs: exynos: Add EXYNOS_UFS_OPT_TIMER_TICK_SELECT option
  scsi: ufs: exynos: Add EXYNOS_UFS_OPT_UFSPR_SECURE option
  scsi: ufs: dt-bindings: exynos: Add gs101 compatible
  scsi: qla2xxx: Fix debugfs output for fw_resource_count
  scsi: qedf: Ensure the copied buf is NUL terminated
  scsi: bfa: Ensure the copied buf is NUL terminated
  ...
Merge patch series "ufs-exynos support for Tensor GS101" 2024-05-07T01:37:20+00:00 Martin K. Petersen martin.petersen@oracle.com 2024-05-07T01:37:20+00:00 0d9a1ec632d3ce343b50d93743b24f73a2889906 Peter Griffin <peter.griffin@linaro.org> says: Hi Martin, James & Alim, This series adds support to the ufs-exynos driver for Tensor gs101 found in Pixel 6. It was send previously in [1] and [2] but included the other clock, phy and DTS parts. This series has been split into just the ufs-exynos part to hopefully make things easier. With this series, plus the phy, clock and dts changes UFS is functional upstream for Pixel 6. The SKhynix HN8T05BZGKX015 can be enumerated, partitions mounted etc. The series is split into some prepatory patches for ufs-exynos and a final patch that adds the gs101 support. Note the sysreg clock has been moved to ufs node as fine grained clock control around the syscon sysreg register accesses doesn't result in functional UFS. regards, Peter Link: https://lore.kernel.org/r/20240426122004.2249178-1-peter.griffin@linaro.org Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> 
Peter Griffin <peter.griffin@linaro.org> says:

Hi Martin, James & Alim,

This series adds support to the ufs-exynos driver for Tensor gs101
found in Pixel 6. It was send previously in [1] and [2] but included
the other clock, phy and DTS parts. This series has been split into
just the ufs-exynos part to hopefully make things easier.

With this series, plus the phy, clock and dts changes UFS is
functional upstream for Pixel 6. The SKhynix HN8T05BZGKX015 can be
enumerated, partitions mounted etc.

The series is split into some prepatory patches for ufs-exynos and a
final patch that adds the gs101 support.

Note the sysreg clock has been moved to ufs node as fine grained clock
control around the syscon sysreg register accesses doesn't result in
functional UFS.

regards,

Peter

Link: https://lore.kernel.org/r/20240426122004.2249178-1-peter.griffin@linaro.org
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
scsi: ufs: exynos: Add support for Tensor gs101 SoC 2024-05-07T01:34:37+00:00 Peter Griffin peter.griffin@linaro.org 2024-04-26T12:20:04+00:00 d11e0a318df84f2542316ec8cc0fa4034240ee66 Add a dedicated compatible and drv_data with associated hooks for gs101 SoC found on Pixel 6. Note we make use of the previously added EXYNOS_UFS_OPT_UFSPR_SECURE option, to skip initialisation of UFSPR registers as these are only accessible via SMC call. EXYNOS_UFS_OPT_TIMER_TICK_SELECT option is also set to select tick source. This has been done so as not to effect any existing platforms. DBG_OPTION_SUITE on gs101 has different address offsets to other SoCs so these register offsets now come from uic_attr struct. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240426122004.2249178-7-peter.griffin@linaro.org Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> 
Add a dedicated compatible and drv_data with associated hooks for gs101 SoC
found on Pixel 6.

Note we make use of the previously added EXYNOS_UFS_OPT_UFSPR_SECURE
option, to skip initialisation of UFSPR registers as these are only
accessible via SMC call.

EXYNOS_UFS_OPT_TIMER_TICK_SELECT option is also set to select tick
source. This has been done so as not to effect any existing platforms.

DBG_OPTION_SUITE on gs101 has different address offsets to other SoCs so
these register offsets now come from uic_attr struct.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240426122004.2249178-7-peter.griffin@linaro.org
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
scsi: ufs: exynos: Add some pa_dbg_ register offsets into drvdata 2024-05-07T01:34:37+00:00 Peter Griffin peter.griffin@linaro.org 2024-04-26T12:20:03+00:00 6f9f0d564b0411f8d86d73c7cb6b2703839e8a96 This allows these registers to be at different offsets or not exist at all on some SoCs variants. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240426122004.2249178-6-peter.griffin@linaro.org Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> 
This allows these registers to be at different offsets or not exist at all
on some SoCs variants.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240426122004.2249178-6-peter.griffin@linaro.org
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
scsi: ufs: exynos: Allow max frequencies up to 267Mhz 2024-05-07T01:34:37+00:00 Peter Griffin peter.griffin@linaro.org 2024-04-26T12:20:02+00:00 c9deb9a4f574b49bfd00be88aba470659d2db671 Platforms such as Tensor gs101 the pclk frequency is 267Mhz. Increase PCLK_AVAIL_MAX so we don't fail the frequency check. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240426122004.2249178-5-peter.griffin@linaro.org Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> 
Platforms such as Tensor gs101 the pclk frequency is 267Mhz.  Increase
PCLK_AVAIL_MAX so we don't fail the frequency check.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240426122004.2249178-5-peter.griffin@linaro.org
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
scsi: ufs: exynos: Add EXYNOS_UFS_OPT_TIMER_TICK_SELECT option 2024-05-07T01:34:37+00:00 Peter Griffin peter.griffin@linaro.org 2024-04-26T12:20:01+00:00 9238cad67969e7001e296eaedcdffc63fc38ab30 This option is intended to be set for SoCs that have HCI_V2P1_CTRL register and can select their tick source via IA_TICK_SEL bit. Source clock selection for timer tick 0x0 = Bus clock (aclk) 0x1 = Function clock (mclk) Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240426122004.2249178-4-peter.griffin@linaro.org Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> 
This option is intended to be set for SoCs that have HCI_V2P1_CTRL register
and can select their tick source via IA_TICK_SEL bit.

Source clock selection for timer tick
0x0 = Bus clock (aclk)
0x1 = Function clock (mclk)

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240426122004.2249178-4-peter.griffin@linaro.org
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
scsi: ufs: exynos: Add EXYNOS_UFS_OPT_UFSPR_SECURE option 2024-05-07T01:34:37+00:00 Peter Griffin peter.griffin@linaro.org 2024-04-26T12:20:00+00:00 449adb00d4f7870eb07adedd34e4a4b69036ec12 This option is intended to be set on platforms whose ufspr registers are only accessible via smc call (such as gs101). Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240426122004.2249178-3-peter.griffin@linaro.org Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> 
This option is intended to be set on platforms whose ufspr registers are
only accessible via smc call (such as gs101).

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240426122004.2249178-3-peter.griffin@linaro.org
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Merge patch series "convert SCSI to atomic queue limits, part 1 (v3)" 2024-04-12T10:35:55+00:00 Martin K. Petersen martin.petersen@oracle.com 2024-04-12T10:35:55+00:00 f92141e18c8b466027e226f3388de15b059b6f65 Christoph Hellwig <hch@lst.de> says: Hi all, this series converts the SCSI midlayer and LLDDs to use atomic queue limits API. It is pretty straight forward, except for the mpt3mr driver which does really weird and probably already broken things by setting limits from unlocked device iteration callbacks. I will probably defer the (more complicated) ULD changes to the next merge window as they would heavily conflict with Damien's zone write plugging series. With that the series could go in through the SCSI tree if Jens' ACKs the core block layer bits. Link: https://lore.kernel.org/r/20240409143748.980206-1-hch@lst.de Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> 
Christoph Hellwig <hch@lst.de> says:

Hi all,

this series converts the SCSI midlayer and LLDDs to use atomic queue
limits API.  It is pretty straight forward, except for the mpt3mr
driver which does really weird and probably already broken things by
setting limits from unlocked device iteration callbacks.

I will probably defer the (more complicated) ULD changes to the next
merge window as they would heavily conflict with Damien's zone write
plugging series.  With that the series could go in through the SCSI
tree if Jens' ACKs the core block layer bits.

Link: https://lore.kernel.org/r/20240409143748.980206-1-hch@lst.de
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
scsi: ufs: mediatek: Fix module autoloading 2024-04-12T01:57:15+00:00 Krzysztof Kozlowski krzysztof.kozlowski@linaro.org 2024-04-09T20:39:54+00:00 a6584df2fd51bc0d1611dd0fc9c48cfca3fd68c7 Add MODULE_DEVICE_TABLE() so the module can be properly autoloaded based on the alias from of_device_id table. Cc: Will McVicker <willmcvicker@google.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240409203954.80484-1-krzysztof.kozlowski@linaro.org Reviewed-by: Will McVicker <willmcvicker@google.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Peter Wang <peter.wang@mediatek.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> 
Add MODULE_DEVICE_TABLE() so the module can be properly autoloaded based on
the alias from of_device_id table.

Cc: Will McVicker <willmcvicker@google.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240409203954.80484-1-krzysztof.kozlowski@linaro.org
Reviewed-by: Will McVicker <willmcvicker@google.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
scsi: ufs: exynos: Support module autoloading 2024-04-12T01:56:11+00:00 Will McVicker willmcvicker@google.com 2024-04-09T20:22:02+00:00 2810702f2cbc5135f97e381edbdff2553e257ca5 Export the module alias information using the MODULE_DEVICE_TABLE() macro in order to support auto-loading this module for devices that support it. $ modinfo -F alias out/linux/drivers/ufs/host/ufs-exynos.ko of:N*T*Ctesla,fsd-ufsC* of:N*T*Ctesla,fsd-ufs of:N*T*Csamsung,exynosautov9-ufs-vhC* of:N*T*Csamsung,exynosautov9-ufs-vh of:N*T*Csamsung,exynosautov9-ufsC* of:N*T*Csamsung,exynosautov9-ufs of:N*T*Csamsung,exynos7-ufsC* of:N*T*Csamsung,exynos7-ufs Signed-off-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20240409202203.1308163-1-willmcvicker@google.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> 
Export the module alias information using the MODULE_DEVICE_TABLE() macro
in order to support auto-loading this module for devices that support it.

$ modinfo -F alias out/linux/drivers/ufs/host/ufs-exynos.ko
of:N*T*Ctesla,fsd-ufsC*
of:N*T*Ctesla,fsd-ufs
of:N*T*Csamsung,exynosautov9-ufs-vhC*
of:N*T*Csamsung,exynosautov9-ufs-vh
of:N*T*Csamsung,exynosautov9-ufsC*
of:N*T*Csamsung,exynosautov9-ufs
of:N*T*Csamsung,exynos7-ufsC*
of:N*T*Csamsung,exynos7-ufs

Signed-off-by: Will McVicker <willmcvicker@google.com>
Link: https://lore.kernel.org/r/20240409202203.1308163-1-willmcvicker@google.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>