linux-toradex.git/drivers/usb/dwc2/core.c, branch v4.1.10

usb: dwc2: Fixed a few typos in comments

2015-01-12T18:13:24+00:00

Fixed 3 typos in comments

Signed-off-by: Mickael Maison 
Signed-off-by: Felipe Balbi

usb: dwc2: Update common interrupt handler to call gadget interrupt handler

2014-11-14T20:59:48+00:00

Make dwc2_handle_common_intr call the gadget interrupt function when operating
in peripheral mode. Remove the spinlock functions in s3c_hsotg_irq as
dwc2_handle_common_intr() already has the spinlocks.

Move the registeration of the IRQ to common code for platform and PCI.

Remove duplicate interrupt conditions that was in gadget, as those are handled
by dwc2 common interrupt handler.

Acked-by: Paul Zimmerman 
Signed-off-by: Dinh Nguyen 
Signed-off-by: Felipe Balbi

usb: dwc2: clip max_transfer_size to 65535

2014-09-19T23:17:58+00:00

Clip max_transfer_size to 65535 for host. dwc2_hc_setup_align_buf()
allocates coherent buffers with this size, and if it's too large we
can exhaust the coherent DMA pool.

Tested on Raspberry Pi and Altera SOCFPGA.

Signed-off-by: Paul Zimmerman 
Signed-off-by: Greg Kroah-Hartman

usb: dwc2: add 'mode' which based on Kconfig select or dts setting

2014-09-08T22:43:28+00:00

According to the "dr_mode", the otg controller can work as
device role and host role. Some boards always want to use host mode
and some other boards want to use gadget mode. We use the dts setting
to set dwc2's mode, rather than fixing it to whatever hardware says.

Signed-off-by: Kever Yang 
Acked-by: Paul Zimmerman 
Tested-by: Doug Anderson 
Signed-off-by: Greg Kroah-Hartman

usb: dwc2: Read GNPTXFSIZ when in forced HOST mode.

2014-09-08T22:41:14+00:00

The documentation for GNPTXFSIZ says that "For host mode, this field
is always valid."  Since we're already switching to host mode for
HPTXFSIZ, let's also read GNPTXFSIZ in host mode.

On an rk3288 SoC, without this change we see this at bootup:
  dwc2 ff580000.usb: gnptxfsiz=00100400
  dwc2 ff580000.usb: 128 invalid for host_nperio_tx_fifo_size. Check HW configuration.

After this change we see:
  dwc2 ff580000.usb: gnptxfsiz=04000400

Signed-off-by: Doug Anderson 
Acked-by: Paul Zimmerman 
Signed-off-by: Greg Kroah-Hartman

usb: dwc2: Add function to calculate correct FIFO sizes

2014-05-27T22:42:42+00:00

The dwc2 IP on the SOCFPGA cannot use the default HW configured
FIFO sizes. The total FIFO depth as read from GHWCFG3 reports 0x1f80 or 8064
32-bit words. But the GRXFSIZ, GNPTXFSIZ, and HPTXFSIZ register defaults
to 0x2000 or 8192 32-bit words. So the driver cannot just use the fifo sizes
as read from those registers.

For platforms that face the same issue, this commits sets the RX, periodic TX,
and non-periodic TX fifo size to those that are recommended v2.93a spec for
the DWC2 IP. Implements Method #2 from the Synopsys v2.93a spec for the DWC2.

Signed-off-by: Dinh Nguyen 
Acked-by: Paul Zimmerman 
Reviewed-by: Felipe Balbi 
Signed-off-by: Greg Kroah-Hartman

usb: dwc2: fix role switch breakage

2014-02-04T20:59:14+00:00

Commit beb7e592bc "staging: dwc2: add check on dwc2_core_reset
return" broke the B -> A role switching on OTG-enabled platforms.
This commit fixes it.

Reported-by: Dinh Nguyen 
Tested-by: Dinh Nguyen 
Signed-off-by: Paul Zimmerman 
Signed-off-by: Greg Kroah-Hartman

Move DWC2 driver out of staging

2014-01-13T22:44:01+00:00

The DWC2 driver should now be in good enough shape to move out of
staging. I have stress tested it overnight on RPI running mass
storage and Ethernet transfers in parallel, and for several days
on our proprietary PCI-based platform.

Signed-off-by: Paul Zimmerman 
Cc: Felipe Balbi 
Signed-off-by: Greg Kroah-Hartman