Add adapter driver for I2C adapter in Coral-P(A)/Lime GDCs.
So we can easily access devices on controller's I2C bus using
i2c-dev interface.

Signed-off-by: Anatolij Gustschin <agust@denx.de>

The driver can be built as either a PCI or platform (OF) driver.  It
might make sense to built it as both (though that is not currently
possible) but it certainly doesn't make sense to build it as neither!
Add dependencies and add a choice group to ensure that exactly one of
FB_MB862XX_PCI_GDC and FB_MB862XX_LIME is selected.

Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (137 commits)
  ARM: bcmring: convert to use sp804 clockevents
  ARM: bcmring: convert to sp804 clocksource
  ARM: 6912/1: bcmring: Add clkdev table in init_early
  clockevents: ARM sp804: obtain sp804 timer rate via clks
  clockevents: ARM sp804: allow clockevent name to be specified
  clocksource: ARM sp804: obtain sp804 timer rate via clks
  clocksource: ARM sp804: allow clocksource name to be specified
  clocksource: convert OMAP1 to 32-bit down counting clocksource
  clocksource: convert MXS timrotv2 to 32-bit down counting clocksource
  clocksource: convert SPEAr platforms 16-bit up counting clocksource
  clocksource: convert Integrator/AP 16-bit down counting clocksource
  clocksource: convert W90x900 24-bit down counting clocksource
  clocksource: convert ARM 32-bit down counting clocksources
  clocksource: convert ARM 32-bit up counting clocksources
  clocksource: add common mmio clocksource
  ARM: update sa1100 to reflect PXA updates
  ARM: omap1: convert to using readl/writel instead of volatile struct
  ARM: omap1: delete useless interrupt handler
  ARM: s5p: consolidate selection of timer register
  ARM: 6939/1: fix missing 'cpu_relax()' declaration
  ...

Based on the patch by Takanari Hayama <taki@igel.co.jp>

Adds support framework necessary to use Media RAM (MERAM)
caching functionality with the LCDC.  The MERAM is accessed
through up to 4 Interconnect Buffers (ICBs).

ICB numbers and MERAM address ranges to use are specified in
by filling in the .meram_cfg member of the LCDC platform data

Signed-off-by: Damian Hobson-Garcia <dhobsong@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

* 'viafb-next' of git://github.com/schandinat/linux-2.6: (24 commits)
  viafb: Automatic OLPC XO-1.5 configuration
  viafb: remove unused CEA mode
  viafb: try to map less memory in case of failure
  viafb: use write combining for video ram
  viafb: add X server compatibility mode
  viafb: reduce OLPC refresh a bit
  viafb: fix OLPC XO 1.5 device connection
  viafb: fix OLPC DCON refresh rate
  viafb: delete clock and PLL initialization
  viafb: replace custom return values
  viafb: some small cleanup for global variables
  viafb: gather common good, old VGA initialization in one place
  viafb: add engine clock support
  viafb: add VIA slapping capability
  viafb: split clock and PLL code to an extra file
  viafb: add primary/secondary clock on/off switches
  viafb: add clock source selection and PLL power management support
  viafb: prepare for PLL separation
  viafb: call viafb_get_clk_value only in viafb_set_vclock
  viafb: remove unused max_hres/vres
  ...

remove usage of CONFIG_ARCH_MX1. It's mostly unused anyway, replace
it with cpu_is_mx1() where necessary. Also, depend on
IMX_HAVE_PLATFORM_IMX_FB instead of the architectures directly.

LAKML-Reference: 20110303141244.GQ29521@pengutronix.de
Acked-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This patch adds a config option to be compatible with X servers like
OpenChrome. This is required as for example the X server does not
handle things like disabled IGAs/PLLs resulting in a potential
freeze on X startup. With this option disabled we can provide some
nice features like power management and not reinitializing the
hardware on every mode switch (taking long time, causing flickering).

Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>

Add I2C support for the DDC bus and also default mode initialization by
reading monitor EDID to the s3fb driver.

Tested on Trio64V+ (2 cards), Trio64V2/DX, Virge (3 cards),
Virge/DX (3 cards), Virge/GX2, Trio3D/2X (4 cards), Trio3D.

Will probably not work on Trio32 - my 2 cards have DDC support in BIOS that
looks different from the other cards but the DDC pins on the VGA connector
are not connected.

Signed-off-by: Ondrej Zary <linux@rainbow-software.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>