linux-toradex.git/include/acpi/actbl1.h, branch v6.18-rc4 Linux kernel for Apalis and Colibri modules Merge tag 'cxl-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl 2025-10-04T19:02:50+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-10-04T19:02:50+00:00 d104e3d17f7bfc505281f57f8c1a5589fca6ffe4 Pull CXL updates from Dave Jiang: "The changes include adding poison injection support, fixing CXL access coordinates when onlining CXL memory, and delaing the enumeration of downstream switch ports for CXL hierarchy to ensure that the CXL link is established at the time of enumeration to address a few issues observed on AMD and Intel platforms. Misc changes: - Use str_plural() instead of open code for emitting strings. - Use str_enabled_disabled() instead of ternary operator - Fix emit of type resource_size_t argument for validate_region_offset() - Typo fixup in CXL driver-api documentation - Rename CFMWS coherency restriction defines - Add convention doc describe dealing with x86 low memory hole and CXL Poison Inject support: - Move hpa_to_spa callback to new reoot decoder ops structure - Define a SPA to HPA callback for interleave calculation with XOR math - Add support for SPA to DPA address translation with XOR - Add locked variants of poison inject and clear functions - Add inject and clear poison support by region offset CXL access coordinates update fix: - A comment update for hotplug memory callback prority defines - Add node_update_perf_attrs() for updating perf attrs on a node - Update cxl_access_coordinates() to use the new node update function - Remove hmat_update_target_coordinates() and related code CXL delayed downstream port enumeration and initialization: - Add helper to detect top of CXL device topology and remove open coding - Add helper to delete single dport - Add a cached copy of target_map to cxl_decoder - Refactor decoder setup to reduce cxl_test burden - Defer dport allocation for switch ports - Add mock version of devm_cxl_add_dport_by_dev() for cxl_test - Adjust the mock version of devm_cxl_switch_port_decoders_setup() due to cxl core usage - Setup target_map for cxl_test decoder initialization - Change SSLBIS handler to handle single dport - Move port register setup to when first dport appears" * tag 'cxl-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (25 commits) cxl: Move port register setup to when first dport appear cxl: Change sslbis handler to only handle single dport cxl/test: Setup target_map for cxl_test decoder initialization cxl/test: Adjust the mock version of devm_cxl_switch_port_decoders_setup() cxl/test: Add mock version of devm_cxl_add_dport_by_dev() cxl: Defer dport allocation for switch ports cxl/test: Refactor decoder setup to reduce cxl_test burden cxl: Add a cached copy of target_map to cxl_decoder cxl: Add helper to delete dport cxl: Add helper to detect top of CXL device topology cxl: Documentation/driver-api/cxl: Describe the x86 Low Memory Hole solution cxl/acpi: Rename CFMW coherency restrictions Documentation/driver-api: Fix typo error in cxl acpi/hmat: Remove now unused hmat_update_target_coordinates() cxl, acpi/hmat: Update CXL access coordinates directly instead of through HMAT drivers/base/node: Add a helper function node_update_perf_attrs() mm/memory_hotplug: Update comment for hotplug memory callback priorities cxl: Fix emit of type resource_size_t argument for validate_region_offset() cxl/region: Add inject and clear poison by region offset cxl/core: Add locked variants of the poison inject and clear funcs ... 
Pull CXL updates from Dave Jiang:
 "The changes include adding poison injection support, fixing CXL access
  coordinates when onlining CXL memory, and delaing the enumeration of
  downstream switch ports for CXL hierarchy to ensure that the CXL link
  is established at the time of enumeration to address a few issues
  observed on AMD and Intel platforms.

  Misc changes:
   - Use str_plural() instead of open code for emitting strings.
   - Use str_enabled_disabled() instead of ternary operator
   - Fix emit of type resource_size_t argument for
     validate_region_offset()
   - Typo fixup in CXL driver-api documentation
   - Rename CFMWS coherency restriction defines
   - Add convention doc describe dealing with x86 low memory hole
     and CXL

  Poison Inject support:
   - Move hpa_to_spa callback to new reoot decoder ops structure
   - Define a SPA to HPA callback for interleave calculation with
     XOR math
   - Add support for SPA to DPA address translation with XOR
   - Add locked variants of poison inject and clear functions
   - Add inject and clear poison support by region offset

  CXL access coordinates update fix:
   - A comment update for hotplug memory callback prority defines
   - Add node_update_perf_attrs() for updating perf attrs on a node
   - Update cxl_access_coordinates() to use the new node update function
   - Remove hmat_update_target_coordinates() and related code

  CXL delayed downstream port enumeration and initialization:
   - Add helper to detect top of CXL device topology and remove
     open coding
   - Add helper to delete single dport
   - Add a cached copy of target_map to cxl_decoder
   - Refactor decoder setup to reduce cxl_test burden
   - Defer dport allocation for switch ports
   - Add mock version of devm_cxl_add_dport_by_dev() for cxl_test
   - Adjust the mock version of devm_cxl_switch_port_decoders_setup()
     due to cxl core usage
   - Setup target_map for cxl_test decoder initialization
   - Change SSLBIS handler to handle single dport
   - Move port register setup to when first dport appears"

* tag 'cxl-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (25 commits)
  cxl: Move port register setup to when first dport appear
  cxl: Change sslbis handler to only handle single dport
  cxl/test: Setup target_map for cxl_test decoder initialization
  cxl/test: Adjust the mock version of devm_cxl_switch_port_decoders_setup()
  cxl/test: Add mock version of devm_cxl_add_dport_by_dev()
  cxl: Defer dport allocation for switch ports
  cxl/test: Refactor decoder setup to reduce cxl_test burden
  cxl: Add a cached copy of target_map to cxl_decoder
  cxl: Add helper to delete dport
  cxl: Add helper to detect top of CXL device topology
  cxl: Documentation/driver-api/cxl: Describe the x86 Low Memory Hole solution
  cxl/acpi: Rename CFMW coherency restrictions
  Documentation/driver-api: Fix typo error in cxl
  acpi/hmat: Remove now unused hmat_update_target_coordinates()
  cxl, acpi/hmat: Update CXL access coordinates directly instead of through HMAT
  drivers/base/node: Add a helper function node_update_perf_attrs()
  mm/memory_hotplug: Update comment for hotplug memory callback priorities
  cxl: Fix emit of type resource_size_t argument for validate_region_offset()
  cxl/region: Add inject and clear poison by region offset
  cxl/core: Add locked variants of the poison inject and clear funcs
  ...
ACPICA: CEDT: Add Back-Invalidate restriction to CXL Window 2025-09-15T10:20:13+00:00 Davidlohr Bueso dave@stgolabs.net 2025-09-12T20:04:04+00:00 eddf12041ddd8c40289015f42285c5ac614b5c30 This is added in newer version (3.0+) of the CXL Spec to support the HDM-DB coherency model. Link: https://github.com/acpica/acpica/commit/a6886da1 Signed-off-by: Davidlohr Bueso <dave@stgolabs.net> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> 
This is added in newer version (3.0+) of the CXL Spec to support the
HDM-DB coherency model.

Link: https://github.com/acpica/acpica/commit/a6886da1
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
cxl/acpi: Rename CFMW coherency restrictions 2025-09-10T15:09:10+00:00 Davidlohr Bueso dave@stgolabs.net 2025-09-08T16:00:34+00:00 c4272905c37930c19b54fa3549b22899122ce69e ACPICA commit 710745713ad3a2543dbfb70e84764f31f0e46bdc This has been renamed in more recent CXL specs, as type3 (memory expanders) can also use HDM-DB for device coherent memory. Link: https://github.com/acpica/acpica/commit/710745713ad3a2543dbfb70e84764f31f0e46bdc Acked-by: Rafael J. Wysocki (Intel) <rafael@kernel.org> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250908160034.86471-1-dave@stgolabs.net Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
ACPICA commit 710745713ad3a2543dbfb70e84764f31f0e46bdc

This has been renamed in more recent CXL specs, as
type3 (memory expanders) can also use HDM-DB for
device coherent memory.

Link: https://github.com/acpica/acpica/commit/710745713ad3a2543dbfb70e84764f31f0e46bdc
Acked-by: Rafael J. Wysocki (Intel) <rafael@kernel.org>
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://patch.msgid.link/20250908160034.86471-1-dave@stgolabs.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
ACPICA: Update copyright year 2025-05-12T13:38:43+00:00 Saket Dumbre saket.dumbre@intel.com 2025-04-04T05:21:13+00:00 0e9fd691a7026580708a5f22f18fca0e58b61899 ACPICA commit 45253be18b3f37d46cd0072aa3f8a0a21a70e0a4 Changes needed by acpisrc to update copyright year when building for release. Link: https://github.com/acpica/acpica/commit/45253be1 Signed-off-by: Saket Dumbre <saket.dumbre@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> 
ACPICA commit 45253be18b3f37d46cd0072aa3f8a0a21a70e0a4

Changes needed by acpisrc to update copyright year when building for
release.

Link: https://github.com/acpica/acpica/commit/45253be1
Signed-off-by: Saket Dumbre <saket.dumbre@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPICA: infrastructure: Add new DMT_BUF types and shorten a long name 2025-05-12T13:38:42+00:00 Tony Luck tony.luck@intel.com 2025-04-25T19:26:44+00:00 5833942db741bb321a8557511969c04481086c81 ACPICA commit b8713f71b4023a0396fe61503bbbf5226e5eed1b Some ERDT subtables have 11 and 24 byte reserved fields. Add the ACPI_DMT_BUF11 and ACPI_DMT_BUF24 types to describe these reserved fields in struct acpi_dmtable_info structures. Shorten the ACPI_SUBTABLE_HEADER_16 name to ACPI_SUBTBL_HDR Link: https://github.com/acpica/acpica/commit/b8713f71 Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/3643286.iIbC2pHGDl@rjwysocki.net 
ACPICA commit b8713f71b4023a0396fe61503bbbf5226e5eed1b

Some ERDT subtables have 11 and 24 byte reserved fields.

Add the ACPI_DMT_BUF11 and ACPI_DMT_BUF24 types to describe these reserved
fields in struct acpi_dmtable_info structures.

Shorten the ACPI_SUBTABLE_HEADER_16 name to ACPI_SUBTBL_HDR

Link: https://github.com/acpica/acpica/commit/b8713f71
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/3643286.iIbC2pHGDl@rjwysocki.net
ACPICA: infrastructure: Add new header and ACPI_DMT_BUF26 types 2025-05-12T13:38:41+00:00 Tony Luck tony.luck@intel.com 2025-04-25T19:23:17+00:00 67f9d690c94ad97f03e055e1444f5471b2d44e4c ACPICA commit 52840d3826bd7e183fcb555e044e190aea0b5021 New MRRM tables can have subtables that are larger than 255 bytes. Add a new header typedef that uses u16 for Length. Could be backported to acpi_aspt_header, struct acpi_dmar_header, struct acpi_nfit_header, struct acpi_prmt_module_header, struct acpi_prmt_module_info. Will be used for upcoming ERDT table. MRRM table has a 26-byte reserved section in header. Add ACPI_DMT_BUF26 to describe this in struct acpi_dmtable_info. Link: https://github.com/acpica/acpica/commit/52840d38 Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/3005638.e9J7NaK4W3@rjwysocki.net 
ACPICA commit 52840d3826bd7e183fcb555e044e190aea0b5021

New MRRM tables can have subtables that are larger than 255 bytes.

Add a new header typedef that uses u16 for Length. Could be
backported to acpi_aspt_header, struct acpi_dmar_header, struct acpi_nfit_header,
struct acpi_prmt_module_header, struct acpi_prmt_module_info. Will be used for
upcoming ERDT table.

MRRM table has a 26-byte reserved section in header. Add ACPI_DMT_BUF26
to describe this in struct acpi_dmtable_info.

Link: https://github.com/acpica/acpica/commit/52840d38
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/3005638.e9J7NaK4W3@rjwysocki.net
ACPICA: Interpret SIDP structures in DMAR 2025-05-12T13:38:41+00:00 Alexey Neyman aneyman@google.com 2025-04-25T19:22:35+00:00 f61c39494901d729d5c21ba92040e9164ea957be ACPICA commit af51f730e0bccf789686cea68e116d5f0b27aacb Added in revision 3.4 of the VT-d spec. To support SIDP, part of the previously reserved field in the device scope structure was used to create a 1-byte "Flags" field. Link: https://github.com/acpica/acpica/commit/af51f730 Signed-off-by: Alexey Neyman <aneyman@google.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/2239745.irdbgypaU6@rjwysocki.net 
ACPICA commit af51f730e0bccf789686cea68e116d5f0b27aacb

Added in revision 3.4 of the VT-d spec. To support SIDP, part of the
previously reserved field in the device scope structure was used to
create a 1-byte "Flags" field.

Link: https://github.com/acpica/acpica/commit/af51f730
Signed-off-by: Alexey Neyman <aneyman@google.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/2239745.irdbgypaU6@rjwysocki.net
ACPICA: actbl1: Add EINJv2 get error type action 2025-03-27T12:17:18+00:00 Zaid Alali zaidal@os.amperecomputing.com 2025-03-26T20:08:46+00:00 56b594fdb6dd68d085067a69f5f78171aa6f1657 ACPICA commit 6975cd07e20ba955556e1eafe8a326834c354ae6 Add EINJV2_GET_ERROR_TYPE as defined in the new specs(1)(2). Link: https://bugzilla.tianocore.org/show_bug.cgi?id=4615 (1) Link: https://bugzilla.tianocore.org/attachment.cgi?id=1446 (2) Link: https://github.com/acpica/acpica/commit/6975cd07 Signed-off-by: Zaid Alali <zaidal@os.amperecomputing.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/3344273.aeNJFYEL58@rjwysocki.net 
ACPICA commit 6975cd07e20ba955556e1eafe8a326834c354ae6

Add EINJV2_GET_ERROR_TYPE as defined in the new specs(1)(2).

Link: https://bugzilla.tianocore.org/show_bug.cgi?id=4615 (1)
Link: https://bugzilla.tianocore.org/attachment.cgi?id=1446 (2)
Link: https://github.com/acpica/acpica/commit/6975cd07
Signed-off-by: Zaid Alali <zaidal@os.amperecomputing.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/3344273.aeNJFYEL58@rjwysocki.net
ACPICA: actbl1: Update values to hex to follow ACPI specs 2025-03-27T12:17:18+00:00 Zaid Alali zaidal@os.amperecomputing.com 2025-03-26T20:07:57+00:00 5d2f7e76b70121fe06fd12315a6ea439e3bf0414 ACPICA commit 0b44ed75fb551bf3fbbbd39ca72bd932872fff20 ACPI specs(1) define Error Injection Actions in hex values. This commit intends to update values from decimal to hex to be consistent with ACPI specs. Link: https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html (1) Link: https://github.com/acpica/acpica/commit/0b44ed75 Signed-off-by: Zaid Alali <zaidal@os.amperecomputing.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/13729719.uLZWGnKmhe@rjwysocki.net 
ACPICA commit 0b44ed75fb551bf3fbbbd39ca72bd932872fff20

ACPI specs(1) define Error Injection Actions in hex values.
This commit intends to update values from decimal to hex to be
consistent with ACPI specs.

Link: https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html (1)
Link: https://github.com/acpica/acpica/commit/0b44ed75
Signed-off-by: Zaid Alali <zaidal@os.amperecomputing.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/13729719.uLZWGnKmhe@rjwysocki.net
ACPI/CDAT: Add CDAT/DSMAS shared and read only flag values 2024-11-08T16:37:30+00:00 Ira Weiny ira.weiny@intel.com 2024-11-07T20:58:20+00:00 d62e2ed065785c9a7837519067e1307e4a24d2c2 The Coherent Device Attribute Table (CDAT) Device Scoped Memory Affinity Structure (DSMAS) version 1.04 [1] defines flags to indicate if a DPA range is read only and/or shared. Add read only and shareable flag definitions. This change was merged in ACPICA via PR 976.[2] Link: https://uefi.org/sites/default/files/resources/Coherent%20Device%20Attribute%20Table_1.04%20published_0.pdf [1] Link: https://github.com/acpica/acpica/pull/976 [2] Cc: Robert Moore <robert.moore@intel.com> Cc: Len Brown <lenb@kernel.org> Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: linux-acpi@vger.kernel.org Cc: acpica-devel@lists.linux.dev Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Ira Weiny <ira.weiny@intel.com> Link: https://patch.msgid.link/20241107-dcd-type2-upstream-v7-2-56a84e66bc36@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
The Coherent Device Attribute Table (CDAT) Device Scoped Memory Affinity
Structure (DSMAS) version 1.04 [1] defines flags to indicate if a DPA range
is read only and/or shared.

Add read only and shareable flag definitions.

This change was merged in ACPICA via PR 976.[2]

Link: https://uefi.org/sites/default/files/resources/Coherent%20Device%20Attribute%20Table_1.04%20published_0.pdf [1]
Link: https://github.com/acpica/acpica/pull/976 [2]
Cc: Robert Moore <robert.moore@intel.com>
Cc: Len Brown <lenb@kernel.org>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: linux-acpi@vger.kernel.org
Cc: acpica-devel@lists.linux.dev
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Link: https://patch.msgid.link/20241107-dcd-type2-upstream-v7-2-56a84e66bc36@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>