linux-toradex.git/include/acpi/actbl1.h, branch v7.0-rc3 Linux kernel for Apalis and Colibri modules ACPICA: Refactor for TPR Base/Limit registers bitmasks 2026-01-15T17:17:50+00:00 Michal Camacho Romero michal.camacho.romero@intel.com 2026-01-14T12:40:06+00:00 e8f614dabd2238e462e4543abd1eb5c59e612836 Link: https://github.com/acpica/acpica/commit/5cb62a1d4970 Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/3193976.CbtlEUcBR6@rafael.j.wysocki 
Link: https://github.com/acpica/acpica/commit/5cb62a1d4970
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/3193976.CbtlEUcBR6@rafael.j.wysocki
ACPICA: Replace TPRn Base and Limit registers 2026-01-15T17:17:50+00:00 Michal Camacho Romero michal.camacho.romero@intel.com 2026-01-14T12:39:10+00:00 3b8907925a7964903955b59d974d98c7ae707d7a Replace TPRn Base and Limit registers with compatible bitmasks for them. Link: https://github.com/acpica/acpica/commit/be91c5813936 Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/1871109.TLkxdtWsSY@rafael.j.wysocki 
Replace TPRn Base and Limit registers with compatible bitmasks for them.

Link: https://github.com/acpica/acpica/commit/be91c5813936
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/1871109.TLkxdtWsSY@rafael.j.wysocki
ACPICA: Align comments in TPRn-related structures 2026-01-15T17:17:50+00:00 Michal Camacho Romero michal.camacho.romero@intel.com 2026-01-14T12:37:19+00:00 691474b1ae63845044a28debe0e06b88a836770b Align comments in ACPI_TPRN_BASE_REG and ACPI_TPRN_LIMIT_REG structures. Link: https://github.com/acpica/acpica/commit/95815d550969 Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/2286538.NgBsaNRSFp@rafael.j.wysocki 
Align comments in ACPI_TPRN_BASE_REG and ACPI_TPRN_LIMIT_REG structures.

Link: https://github.com/acpica/acpica/commit/95815d550969
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/2286538.NgBsaNRSFp@rafael.j.wysocki
ACPICA: Cleanup comments and DTPR Table handle functions 2026-01-15T17:17:49+00:00 Michal Camacho Romero michal.camacho.romero@intel.com 2026-01-14T12:36:32+00:00 9b02cf9ee67b284020d051da126694d555977e12 Link: https://github.com/acpica/acpica/commit/cc480264335e Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/2042656.yKVeVyVuyW@rafael.j.wysocki 
Link: https://github.com/acpica/acpica/commit/cc480264335e
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/2042656.yKVeVyVuyW@rafael.j.wysocki
ACPICA: Verify DTPR and TPR Instance buffer pointers 2026-01-15T17:17:49+00:00 Michal Camacho Romero michal.camacho.romero@intel.com 2026-01-14T12:35:31+00:00 9565d4713ba6d3711d7b47fee9dde6725721ac06 Verify DTPR and TPR Instance buffer pointers and refactor comments. Link: https://github.com/acpica/acpica/commit/bdec5b61cf5b Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/884204745.0ifERbkFSE@rafael.j.wysocki 
Verify DTPR and TPR Instance buffer pointers and refactor comments.

Link: https://github.com/acpica/acpica/commit/bdec5b61cf5b
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/884204745.0ifERbkFSE@rafael.j.wysocki
ACPICA: Fix Segmentation Fault error related to DTPR 2026-01-15T17:17:49+00:00 Michal Camacho Romero michal.camacho.romero@intel.com 2026-01-14T12:34:43+00:00 b110e28c3bf52c984c232ee633139ea10f754c0c Fix Segmentation Fault error, caused by invalid buffer lenght in DTPR Table Template: * Update buffer length for TPR Table, which invalid value caused Segmentation Fault, during ASL file production. * Refactor invalid values of TPR instances, arrays and serialization requests count and TPR Base addresses in the DTPR table template. * Fix offset updating in the acpi_dm_dump_dtpr function. Link: https://github.com/acpica/acpica/commit/f75850bc4717 Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/2541195.jE0xQCEvom@rafael.j.wysocki 
Fix Segmentation Fault error, caused by invalid buffer lenght in DTPR
Table Template:

 * Update buffer length for TPR Table, which invalid value caused
   Segmentation Fault, during ASL file production.

 * Refactor invalid values of TPR instances, arrays and serialization
   requests count and TPR Base addresses in the DTPR table template.

 * Fix offset updating in the acpi_dm_dump_dtpr function.

Link: https://github.com/acpica/acpica/commit/f75850bc4717
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/2541195.jE0xQCEvom@rafael.j.wysocki
ACPICA: Create auxiliary ACPI_TPR_AUX_SR structure for iASL compiler 2026-01-15T17:17:49+00:00 Michal Camacho Romero michal.camacho.romero@intel.com 2026-01-14T12:33:49+00:00 6f99d3fe224feefabc012869e10cbff52eb5f5f8 Define unofficial structure ACPI_TPR_AUX_SR, which holds information about the number of serialization registers for TPRs. It simplifies DTPR Serialization Request Info Table compilation. Link: https://github.com/acpica/acpica/commit/31f470e708a9 Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/2266165.Icojqenx9y@rafael.j.wysocki 
Define unofficial structure ACPI_TPR_AUX_SR, which holds information
about the number of serialization registers for TPRs.

It simplifies DTPR Serialization Request Info Table compilation.

Link: https://github.com/acpica/acpica/commit/31f470e708a9
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/2266165.Icojqenx9y@rafael.j.wysocki
ACPICA: Define DTPR structure related info tables and data template 2026-01-15T17:17:48+00:00 Michal Camacho Romero michal.camacho.romero@intel.com 2026-01-14T12:24:38+00:00 30c2a333aa90c4265bed7629980eb0df72f56dfb * DTPR Table Info * TPR Instance Table Info * TPR Array Table Info * TPR Serialize Request Table Info * DTPR Table Data Template Link: https://github.com/acpica/acpica/commit/abadf1d34732 Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/3676546.iIbC2pHGDl@rafael.j.wysocki 
 * DTPR Table Info
 * TPR Instance Table Info
 * TPR Array Table Info
 * TPR Serialize Request Table Info
 * DTPR Table Data Template

Link: https://github.com/acpica/acpica/commit/abadf1d34732
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/3676546.iIbC2pHGDl@rafael.j.wysocki
ACPICA: Add DTPR table support for the ASL compiler 2026-01-15T17:17:48+00:00 Michal Camacho Romero michal.camacho.romero@intel.com 2026-01-14T12:23:40+00:00 c5ecbc65bb2287b66b3b8adbdbe0fddb81bc297f Define DTPR related structures offsets. Link: https://github.com/acpica/acpica/commit/c6fc16c8936d Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/7902293.EvYhyI6sBW@rafael.j.wysocki 
Define DTPR related structures offsets.

Link: https://github.com/acpica/acpica/commit/c6fc16c8936d
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/7902293.EvYhyI6sBW@rafael.j.wysocki
ACPICA: Add support for the new ACPI Table: DTPR 2026-01-15T17:17:47+00:00 Michal Camacho Romero michal.camacho.romero@intel.com 2026-01-14T12:16:23+00:00 d6f6bae3ecba665e18a6b6cfcd575f8e9f46b204 Define a new the ACPI Table, structure and registers, related with it, according to the latest version of the Intel TXT DMA Protection Ranges (TPR) specification (Revision 0.73): * DTPR ACPI Table * TPR Base Register * TPR Serialize Request Register * TPR Limit Register * TPR Instance Structure * DMAR TXT Protected Reporting Structure These structures will be used to handle TPRs on the Intel CPU's. Link: https://github.com/acpica/acpica/commit/10e7a88f70da Link: https://uefi.org/sites/default/files/resources/633933_Intel_TXT_DMA_Protection_Ranges_rev_0p73.pdf Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/6234415.lOV4Wx5bFT@rafael.j.wysocki 
Define a new the ACPI Table, structure and registers, related with it, according
to the latest version of the Intel TXT DMA Protection Ranges (TPR) specification
(Revision 0.73):

*    DTPR ACPI Table
*    TPR Base Register
*    TPR Serialize Request Register
*    TPR Limit Register
*    TPR Instance Structure
*    DMAR TXT Protected Reporting Structure

These structures will be used to handle TPRs on the Intel CPU's.

Link: https://github.com/acpica/acpica/commit/10e7a88f70da
Link: https://uefi.org/sites/default/files/resources/633933_Intel_TXT_DMA_Protection_Ranges_rev_0p73.pdf
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/6234415.lOV4Wx5bFT@rafael.j.wysocki