linux-toradex.git/include/acpi/actbl2.h, branch v6.10 Linux kernel for Apalis and Colibri modules Merge branches 'acpi-scan' and 'acpi-tables' 2024-05-13T17:31:06+00:00 Rafael J. Wysocki rafael.j.wysocki@intel.com 2024-05-13T17:31:06+00:00 784cf44945e3408bd87776bd2974b5c7cfc0ced4 Merge ACPI device enumeration changes and ACPI data-only tables support updates for 6.10: - Rearrange fields in several structures to effectively eliminate computations from container_of() in some cases (Andy Shevchenko). - Do some assorted cleanups of the ACPI device enumeration code (Andy Shevchenko). - Make the ACPI device enumeration code skip devices with _STA values clearly identified by the specification as invalid (Rafael Wysocki). - Rework the handling of the NHLT table to simplify and clarify it and drop some obsolete pieces (Cezary Rojewski). * acpi-scan: ACPI: scan: Avoid enumerating devices with clearly invalid _STA values ACPI: scan: Introduce typedef:s for struct acpi_hotplug_context members ACPI: scan: Use standard error checking pattern ACPI: scan: Move misleading comment to acpi_dma_configure_id() ACPI: scan: Use list_first_entry_or_null() in acpi_device_hid() ACPI: bus: Don't use "proxy" headers ACPI: bus: Make container_of() no-op where it makes sense * acpi-tables: ACPI: NHLT: Streamline struct naming ACPI: NHLT: Drop redundant types ACPI: NHLT: Introduce API for the table ACPI: NHLT: Reintroduce types the table consists of 
Merge ACPI device enumeration changes and ACPI data-only tables support
updates for 6.10:

 - Rearrange fields in several structures to effectively eliminate
   computations from container_of() in some cases (Andy Shevchenko).

 - Do some assorted cleanups of the ACPI device enumeration code (Andy
   Shevchenko).

 - Make the ACPI device enumeration code skip devices with _STA values
   clearly identified by the specification as invalid (Rafael Wysocki).

 - Rework the handling of the NHLT table to simplify and clarify it and
   drop some obsolete pieces (Cezary Rojewski).

* acpi-scan:
  ACPI: scan: Avoid enumerating devices with clearly invalid _STA values
  ACPI: scan: Introduce typedef:s for struct acpi_hotplug_context members
  ACPI: scan: Use standard error checking pattern
  ACPI: scan: Move misleading comment to acpi_dma_configure_id()
  ACPI: scan: Use list_first_entry_or_null() in acpi_device_hid()
  ACPI: bus: Don't use "proxy" headers
  ACPI: bus: Make container_of() no-op where it makes sense

* acpi-tables:
  ACPI: NHLT: Streamline struct naming
  ACPI: NHLT: Drop redundant types
  ACPI: NHLT: Introduce API for the table
  ACPI: NHLT: Reintroduce types the table consists of
ACPICA: AEST: Add support for the AEST V2 table 2024-04-30T19:19:58+00:00 Ruidong Tian tianruidong@linux.alibaba.com 2024-04-25T09:34:26+00:00 e049249013b13297817a1b0a33bbedec0ebca293 ACPICA commit ebb49799c78891cbe370f1264844664a3d8b6f35 AEST V2 was published[1], add V2 support based on AEST V1. [1]: https://developer.arm.com/documentation/den0085/latest/ Link: https://github.com/acpica/acpica/commit/ebb4979 Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> 
ACPICA commit ebb49799c78891cbe370f1264844664a3d8b6f35

AEST V2 was published[1], add V2 support based on AEST V1.

[1]: https://developer.arm.com/documentation/den0085/latest/

Link: https://github.com/acpica/acpica/commit/ebb4979
Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPICA: ACPI 6.5: RAS2: Add support for RAS2 table 2024-04-12T13:11:24+00:00 Shiju Jose shiju.jose@huawei.com 2023-09-27T16:41:52+00:00 2e94dc11898042eb528eda3e09db242529722916 ACPICA commit c581606cf49b7574d29c02b1a3bc144650375e32 Add support for ACPI RAS2 feature table(RAS2) defined in the ACPI 6.5 Specification & upwards revision, section 5.2.21. The RAS2 table provides interfaces for platform RAS features. RAS2 offers the same services as RASF, but is more scalable than the latter. RAS2 supports independent RAS controls and capabilities for a given RAS feature for multiple instances of the same component in a given system. The platform can support either RAS2 or RASF but not both. Link: https://github.com/acpica/acpica/commit/c581606c Signed-off-by: Shiju Jose <shiju.jose@huawei.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> 
ACPICA commit c581606cf49b7574d29c02b1a3bc144650375e32

Add support for ACPI RAS2 feature table(RAS2) defined in the ACPI 6.5
Specification & upwards revision, section 5.2.21.

The RAS2 table provides interfaces for platform RAS features. RAS2 offers
the same services as RASF, but is more scalable than the latter.
RAS2 supports independent RAS controls and capabilities for a given RAS
feature for multiple instances of the same component in a given system.
The platform can support either RAS2 or RASF but not both.

Link: https://github.com/acpica/acpica/commit/c581606c
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPI: NHLT: Streamline struct naming 2024-03-27T15:36:45+00:00 Cezary Rojewski cezary.rojewski@intel.com 2024-03-19T08:30:18+00:00 a640acab545b21ed1f347376f34d34e461ea92ba Few recently introduced structs are named 'nhlt2' instead of 'nhlt' to avoid naming conflicts. With duplicate types gone, the conflicts are no more. Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> 
Few recently introduced structs are named 'nhlt2' instead of 'nhlt' to
avoid naming conflicts. With duplicate types gone, the conflicts are no
more.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPI: NHLT: Drop redundant types 2024-03-27T15:36:45+00:00 Cezary Rojewski cezary.rojewski@intel.com 2024-03-19T08:30:17+00:00 659a9490ccfbfad4aa5ab351f8a6f5f83ce5ed6c ACPICA commit 0c7379eae2a0342bfc36d6b7db0bb90ad13a5a3e There are no users for the duplicated NHLT table components. Link: https://github.com/acpica/acpica/pull/890 Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> 
ACPICA commit 0c7379eae2a0342bfc36d6b7db0bb90ad13a5a3e

There are no users for the duplicated NHLT table components.

Link: https://github.com/acpica/acpica/pull/890
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPI: NHLT: Reintroduce types the table consists of 2024-03-27T15:36:45+00:00 Cezary Rojewski cezary.rojewski@intel.com 2024-03-19T08:30:15+00:00 2f7d7ea44adbe7497b225bbb7bfc29e3c792094d ACPICA commit 32260f5ce519e854546ce907fc0cc449e1fe51fe Non HDAudio Link Table (NHLT) is designed to separate hardware-related description (registers) from AudioDSP firmware-related one i.e.: pipelines and modules that together make up the audio stream on Intel DSPs. This task is important as same set of hardware registers can be used with different topologies and vice versa, same topology could be utilized with different set of hardware. As the hardware registers description is directly tied to specific platform, intention is to have such description part of low-level firmware e.g.: BIOS. The initial design has been provided in early Sky Lake (SKL) days. The audio architecture goes by the name cAVS. SKL is a representative of cAVS 1.5. The table helps describe endpoint capabilities ever since. While Raptor Lake (RPL) is the last of cAVS architecture - cAVS 2.5 to be precise - its successor, the ACE architecture which begun with Meteor Lake (MTL) inherited the design for all I2S and PDM configurations. These two configurations are the primary targets for NHLT table. Due to naming conflicts with existing code, several structs are named 'nhlt2' rather than 'nhlt'. Follow up changes clean this up once existing code has no users and is removed. Link: https://github.com/acpica/acpica/pull/912 Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> 
ACPICA commit 32260f5ce519e854546ce907fc0cc449e1fe51fe

Non HDAudio Link Table (NHLT) is designed to separate hardware-related
description (registers) from AudioDSP firmware-related one i.e.:
pipelines and modules that together make up the audio stream on Intel
DSPs. This task is important as same set of hardware registers can be
used with different topologies and vice versa, same topology could be
utilized with different set of hardware. As the hardware registers
description is directly tied to specific platform, intention is to have
such description part of low-level firmware e.g.: BIOS.

The initial design has been provided in early Sky Lake (SKL) days. The
audio architecture goes by the name cAVS. SKL is a representative of
cAVS 1.5. The table helps describe endpoint capabilities ever since.
While Raptor Lake (RPL) is the last of cAVS architecture - cAVS 2.5 to
be precise - its successor, the ACE architecture which begun with
Meteor Lake (MTL) inherited the design for all I2S and PDM
configurations. These two configurations are the primary targets for
NHLT table.

Due to naming conflicts with existing code, several structs are named
'nhlt2' rather than 'nhlt'. Follow up changes clean this up once
existing code has no users and is removed.

Link: https://github.com/acpica/acpica/pull/912
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPICA: MADT: Add new MADT GICC/GICR/ITS non-coherent flags handling 2024-01-09T14:25:37+00:00 Lorenzo Pieralisi lpieralisi@kernel.org 2023-12-27T11:00:37+00:00 3be8fb1bc6fc10b6c8e79052126fa5a423698fd1 ACPICA commit c5d2010744b1bf7efba0bd04a8a9c200ef8fb610 Add new flags and related fields to the MADT GICC/GICR/ITS structures according to the code first ECR: https://bugzilla.tianocore.org/show_bug.cgi?id=4557 Update the MADT template to the latest MADT revision. Link: https://github.com/acpica/acpica/commit/c5d20107 Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> 
ACPICA commit c5d2010744b1bf7efba0bd04a8a9c200ef8fb610

Add new flags and related fields to the MADT GICC/GICR/ITS
structures according to the code first ECR:

https://bugzilla.tianocore.org/show_bug.cgi?id=4557

Update the MADT template to the latest MADT revision.

Link: https://github.com/acpica/acpica/commit/c5d20107
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPICA: MADT: Add GICC online capable bit handling 2024-01-09T14:25:37+00:00 Lorenzo Pieralisi lpieralisi@kernel.org 2023-12-27T11:00:36+00:00 cb1210a7c03c55f9fb7496bd44155c6a024fe458 ACPICA commit 16f0befdeddf25756f317907798192bbaa417e5e Implement code to handle the GICC online capable bit management added into ACPI v6.5. Link: https://github.com/acpica/acpica/commit/16f0befd Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> 
ACPICA commit 16f0befdeddf25756f317907798192bbaa417e5e

Implement code to handle the GICC online capable bit management
added into ACPI v6.5.

Link: https://github.com/acpica/acpica/commit/16f0befd
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPICA: RHCT: Add flags, CMO and MMU nodes 2023-07-10T16:49:16+00:00 Sunil V L sunilvl@ventanamicro.com 2023-04-15T14:47:54+00:00 fe85f8ff2fc99897c62e3d327f853742231647fb ACPICA commit 2eded5a6a13d892b7dc3be6096e7b1e8d4407600 Update RHCT table with below details. 1) Add additional structure to describe the Cache Management Operation (CMO) related information. 2) Add structure to describe MMU type. 3) Convert the current reserved field to flags and define a flag to indicate timer capability. This codefirst ECR is approved by UEFI forum and will be part of next ACPI spec version. Link: https://github.com/acpica/acpica/commit/2eded5a6 Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> 
ACPICA commit 2eded5a6a13d892b7dc3be6096e7b1e8d4407600

Update RHCT table with below details.

 1) Add additional structure to describe the Cache Management
    Operation (CMO) related information.

 2) Add structure to describe MMU type.

 3) Convert the current reserved field to flags and define
    a flag to indicate timer capability.

This codefirst ECR is approved by UEFI forum and will
be part of next ACPI spec version.

Link: https://github.com/acpica/acpica/commit/2eded5a6
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
ACPICA: MADT: Add RISC-V external interrupt controllers 2023-07-10T16:49:16+00:00 Sunil V L sunilvl@ventanamicro.com 2023-04-15T13:49:16+00:00 f3b19adef6c63c2b0778fe5918f786248a9ff897 ACPICA commit 8c048cee4ea7b9ded8db3e1b3b9c14e21e084a2c This adds 3 different external interrupt controller definitions in MADT for RISC-V. 1) RISC-V PLIC is a platform interrupt controller for handling wired interrupt in a RISC-V systems. 2) RISC-V IMSIC is MSI interrupt controller to support MSI interrupts. 3) RISC-V APLIC has dual functionality. First it can act like PLIC and direct all wired interrupts to the CPU which doesn't have MSI controller. Second, when the CPU has MSI controller (IMSIC), it will act as a converter from wired interrupts to MSI. Update the existing RINTC structure also to support these external interrupt controllers. This codefirst ECR is approved by UEFI forum and will be part of next ACPI spec version. Link: https://github.com/acpica/acpica/commit/8c048cee Signed-off-by: Haibo, Xu <haibo1.xu@intel.com> Co-developed-by: Haibo, Xu <haibo1.xu@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> 
ACPICA commit 8c048cee4ea7b9ded8db3e1b3b9c14e21e084a2c

This adds 3 different external interrupt controller
definitions in MADT for RISC-V.

 1) RISC-V PLIC is a platform interrupt controller for
    handling wired interrupt in a RISC-V systems.

 2) RISC-V IMSIC is MSI interrupt controller to
    support MSI interrupts.

 3) RISC-V APLIC has dual functionality. First it can
    act like PLIC and direct all wired interrupts to
    the CPU which doesn't have MSI controller. Second,
    when the CPU has MSI controller (IMSIC), it will
    act as a converter from wired interrupts to MSI.

Update the existing RINTC structure also to support
these external interrupt controllers.

This codefirst ECR is approved by UEFI forum and will
be part of next ACPI spec version.

Link: https://github.com/acpica/acpica/commit/8c048cee
Signed-off-by: Haibo, Xu <haibo1.xu@intel.com>
Co-developed-by: Haibo, Xu <haibo1.xu@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>