<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/include/acpi/actbl2.h, branch v6.14</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>ACPICA: IORT: Update for revision E.f</title>
<updated>2024-11-05T10:24:16+00:00</updated>
<author>
<name>Nicolin Chen</name>
<email>nicolinc@nvidia.com</email>
</author>
<published>2024-10-31T00:20:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=1b8655bb8d977ca110436c1cd0ca957c19670c1e'/>
<id>1b8655bb8d977ca110436c1cd0ca957c19670c1e</id>
<content type='text'>
ACPICA commit c4f5c083d24df9ddd71d5782c0988408cf0fc1ab

The IORT spec, Issue E.f (April 2024), adds a new CANWBS bit to the Memory
Access Flag field in the Memory Access Properties table, mainly for a PCI
Root Complex.

This CANWBS defines the coherency of memory accesses to be not marked IOWB
cacheable/shareable. Its value further implies the coherency impact from a
pair of mismatched memory attributes (e.g. in a nested translation case):
  0x0: Use of mismatched memory attributes for accesses made by this
       device may lead to a loss of coherency.
  0x1: Coherency of accesses made by this device to locations in
       Conventional memory are ensured as follows, even if the memory
       attributes for the accesses presented by the device or provided by
       the SMMU are different from Inner and Outer Write-back cacheable,
       Shareable.

Link: https://github.com/acpica/acpica/commit/c4f5c083
Acked-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Signed-off-by: Nicolin Chen &lt;nicolinc@nvidia.com&gt;
Acked-by: Hanjun Guo &lt;guohanjun@huawei.com&gt;
Tested-by: Nicolin Chen &lt;nicolinc@nvidia.com&gt;
Reviewed-by: Jerry Snitselaar &lt;jsnitsel@redhat.com&gt;
Reviewed-by: Donald Dutile &lt;ddutile@redhat.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
Link: https://lore.kernel.org/r/2-v4-9e99b76f3518+3a8-smmuv3_nesting_jgg@nvidia.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
ACPICA commit c4f5c083d24df9ddd71d5782c0988408cf0fc1ab

The IORT spec, Issue E.f (April 2024), adds a new CANWBS bit to the Memory
Access Flag field in the Memory Access Properties table, mainly for a PCI
Root Complex.

This CANWBS defines the coherency of memory accesses to be not marked IOWB
cacheable/shareable. Its value further implies the coherency impact from a
pair of mismatched memory attributes (e.g. in a nested translation case):
  0x0: Use of mismatched memory attributes for accesses made by this
       device may lead to a loss of coherency.
  0x1: Coherency of accesses made by this device to locations in
       Conventional memory are ensured as follows, even if the memory
       attributes for the accesses presented by the device or provided by
       the SMMU are different from Inner and Outer Write-back cacheable,
       Shareable.

Link: https://github.com/acpica/acpica/commit/c4f5c083
Acked-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Signed-off-by: Nicolin Chen &lt;nicolinc@nvidia.com&gt;
Acked-by: Hanjun Guo &lt;guohanjun@huawei.com&gt;
Tested-by: Nicolin Chen &lt;nicolinc@nvidia.com&gt;
Reviewed-by: Jerry Snitselaar &lt;jsnitsel@redhat.com&gt;
Reviewed-by: Donald Dutile &lt;ddutile@redhat.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
Link: https://lore.kernel.org/r/2-v4-9e99b76f3518+3a8-smmuv3_nesting_jgg@nvidia.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ACPICA: MPAM: Correct the typo in struct acpi_mpam_msc_node member</title>
<updated>2024-08-29T15:48:53+00:00</updated>
<author>
<name>Punit Agrawal</name>
<email>punit.agrawal@bytedance.com</email>
</author>
<published>2024-02-07T19:54:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=cf94e10a037c337559bf6c5486cc1abdf4900a08'/>
<id>cf94e10a037c337559bf6c5486cc1abdf4900a08</id>
<content type='text'>
ACPICA commit 3da3f7d776d17e9bfbb15de88317de8d7397ce38

A member of the struct acpi_mpam_msc_node that represents a Memory System
Controller node structure - num_resource_nodes has a typo. Fix the typo

No functional change.

Link: https://github.com/acpica/acpica/commit/3da3f7d7
Signed-off-by: Punit Agrawal &lt;punit.agrawal@bytedance.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
ACPICA commit 3da3f7d776d17e9bfbb15de88317de8d7397ce38

A member of the struct acpi_mpam_msc_node that represents a Memory System
Controller node structure - num_resource_nodes has a typo. Fix the typo

No functional change.

Link: https://github.com/acpica/acpica/commit/3da3f7d7
Signed-off-by: Punit Agrawal &lt;punit.agrawal@bytedance.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86/acpi: Add support for CPU offlining for ACPI MADT wakeup method</title>
<updated>2024-06-17T15:46:25+00:00</updated>
<author>
<name>Kirill A. Shutemov</name>
<email>kirill.shutemov@linux.intel.com</email>
</author>
<published>2024-06-14T09:59:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=1ceebe2e46720de02af4cf626dc847ecc4a263fd'/>
<id>1ceebe2e46720de02af4cf626dc847ecc4a263fd</id>
<content type='text'>
MADT Multiprocessor Wakeup structure version 1 brings support for CPU offlining:
BIOS provides a reset vector where the CPU has to jump to for offlining itself.
The new TEST mailbox command can be used to test whether the CPU offlined itself
which means the BIOS has control over the CPU and can online it again via the
ACPI MADT wakeup method.

Add CPU offlining support for the ACPI MADT wakeup method by implementing custom
cpu_die(), play_dead() and stop_this_cpu() SMP operations.

CPU offlining makes it possible to hand over secondary CPUs over kexec, not
limiting the second kernel to a single CPU.

The change conforms to the approved ACPI spec change proposal. See the Link.

Signed-off-by: Kirill A. Shutemov &lt;kirill.shutemov@linux.intel.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Reviewed-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
Reviewed-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Kai Huang &lt;kai.huang@intel.com&gt;
Acked-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Tested-by: Tao Liu &lt;ltao@redhat.com&gt;
Link: https://lore.kernel.org/all/13356251.uLZWGnKmhe@kreacher
Link: https://lore.kernel.org/r/20240614095904.1345461-19-kirill.shutemov@linux.intel.com
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
MADT Multiprocessor Wakeup structure version 1 brings support for CPU offlining:
BIOS provides a reset vector where the CPU has to jump to for offlining itself.
The new TEST mailbox command can be used to test whether the CPU offlined itself
which means the BIOS has control over the CPU and can online it again via the
ACPI MADT wakeup method.

Add CPU offlining support for the ACPI MADT wakeup method by implementing custom
cpu_die(), play_dead() and stop_this_cpu() SMP operations.

CPU offlining makes it possible to hand over secondary CPUs over kexec, not
limiting the second kernel to a single CPU.

The change conforms to the approved ACPI spec change proposal. See the Link.

Signed-off-by: Kirill A. Shutemov &lt;kirill.shutemov@linux.intel.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Reviewed-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
Reviewed-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Kai Huang &lt;kai.huang@intel.com&gt;
Acked-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Tested-by: Tao Liu &lt;ltao@redhat.com&gt;
Link: https://lore.kernel.org/all/13356251.uLZWGnKmhe@kreacher
Link: https://lore.kernel.org/r/20240614095904.1345461-19-kirill.shutemov@linux.intel.com
</pre>
</div>
</content>
</entry>
<entry>
<title>x86/acpi: Rename fields in the acpi_madt_multiproc_wakeup structure</title>
<updated>2024-06-17T15:46:15+00:00</updated>
<author>
<name>Kirill A. Shutemov</name>
<email>kirill.shutemov@linux.intel.com</email>
</author>
<published>2024-06-14T09:58:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=6630cbce7cd7785f76b1055f33a71199ef28510b'/>
<id>6630cbce7cd7785f76b1055f33a71199ef28510b</id>
<content type='text'>
In order to support MADT wakeup structure version 1, provide more appropriate
names for the fields in the structure.

Rename 'mailbox_version' to 'version'. This field signifies the version of the
structure and the related protocols, rather than the version of the mailbox.
This field has not been utilized in the code thus far.

Rename 'base_address' to 'mailbox_address' to clarify the kind of address it
represents. In version 1, the structure includes the reset vector address. Clear
and distinct naming helps to prevent any confusion.

Signed-off-by: Kirill A. Shutemov &lt;kirill.shutemov@linux.intel.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Reviewed-by: Kai Huang &lt;kai.huang@intel.com&gt;
Reviewed-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
Reviewed-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Tested-by: Tao Liu &lt;ltao@redhat.com&gt;
Link: https://lore.kernel.org/r/20240614095904.1345461-15-kirill.shutemov@linux.intel.com
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In order to support MADT wakeup structure version 1, provide more appropriate
names for the fields in the structure.

Rename 'mailbox_version' to 'version'. This field signifies the version of the
structure and the related protocols, rather than the version of the mailbox.
This field has not been utilized in the code thus far.

Rename 'base_address' to 'mailbox_address' to clarify the kind of address it
represents. In version 1, the structure includes the reset vector address. Clear
and distinct naming helps to prevent any confusion.

Signed-off-by: Kirill A. Shutemov &lt;kirill.shutemov@linux.intel.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Reviewed-by: Kai Huang &lt;kai.huang@intel.com&gt;
Reviewed-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
Reviewed-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Tested-by: Tao Liu &lt;ltao@redhat.com&gt;
Link: https://lore.kernel.org/r/20240614095904.1345461-15-kirill.shutemov@linux.intel.com
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branches 'acpi-scan' and 'acpi-tables'</title>
<updated>2024-05-13T17:31:06+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2024-05-13T17:31:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=784cf44945e3408bd87776bd2974b5c7cfc0ced4'/>
<id>784cf44945e3408bd87776bd2974b5c7cfc0ced4</id>
<content type='text'>
Merge ACPI device enumeration changes and ACPI data-only tables support
updates for 6.10:

 - Rearrange fields in several structures to effectively eliminate
   computations from container_of() in some cases (Andy Shevchenko).

 - Do some assorted cleanups of the ACPI device enumeration code (Andy
   Shevchenko).

 - Make the ACPI device enumeration code skip devices with _STA values
   clearly identified by the specification as invalid (Rafael Wysocki).

 - Rework the handling of the NHLT table to simplify and clarify it and
   drop some obsolete pieces (Cezary Rojewski).

* acpi-scan:
  ACPI: scan: Avoid enumerating devices with clearly invalid _STA values
  ACPI: scan: Introduce typedef:s for struct acpi_hotplug_context members
  ACPI: scan: Use standard error checking pattern
  ACPI: scan: Move misleading comment to acpi_dma_configure_id()
  ACPI: scan: Use list_first_entry_or_null() in acpi_device_hid()
  ACPI: bus: Don't use "proxy" headers
  ACPI: bus: Make container_of() no-op where it makes sense

* acpi-tables:
  ACPI: NHLT: Streamline struct naming
  ACPI: NHLT: Drop redundant types
  ACPI: NHLT: Introduce API for the table
  ACPI: NHLT: Reintroduce types the table consists of
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Merge ACPI device enumeration changes and ACPI data-only tables support
updates for 6.10:

 - Rearrange fields in several structures to effectively eliminate
   computations from container_of() in some cases (Andy Shevchenko).

 - Do some assorted cleanups of the ACPI device enumeration code (Andy
   Shevchenko).

 - Make the ACPI device enumeration code skip devices with _STA values
   clearly identified by the specification as invalid (Rafael Wysocki).

 - Rework the handling of the NHLT table to simplify and clarify it and
   drop some obsolete pieces (Cezary Rojewski).

* acpi-scan:
  ACPI: scan: Avoid enumerating devices with clearly invalid _STA values
  ACPI: scan: Introduce typedef:s for struct acpi_hotplug_context members
  ACPI: scan: Use standard error checking pattern
  ACPI: scan: Move misleading comment to acpi_dma_configure_id()
  ACPI: scan: Use list_first_entry_or_null() in acpi_device_hid()
  ACPI: bus: Don't use "proxy" headers
  ACPI: bus: Make container_of() no-op where it makes sense

* acpi-tables:
  ACPI: NHLT: Streamline struct naming
  ACPI: NHLT: Drop redundant types
  ACPI: NHLT: Introduce API for the table
  ACPI: NHLT: Reintroduce types the table consists of
</pre>
</div>
</content>
</entry>
<entry>
<title>ACPICA: AEST: Add support for the AEST V2 table</title>
<updated>2024-04-30T19:19:58+00:00</updated>
<author>
<name>Ruidong Tian</name>
<email>tianruidong@linux.alibaba.com</email>
</author>
<published>2024-04-25T09:34:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=e049249013b13297817a1b0a33bbedec0ebca293'/>
<id>e049249013b13297817a1b0a33bbedec0ebca293</id>
<content type='text'>
ACPICA commit ebb49799c78891cbe370f1264844664a3d8b6f35

AEST V2 was published[1], add V2 support based on AEST V1.

[1]: https://developer.arm.com/documentation/den0085/latest/

Link: https://github.com/acpica/acpica/commit/ebb4979
Signed-off-by: Ruidong Tian &lt;tianruidong@linux.alibaba.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
ACPICA commit ebb49799c78891cbe370f1264844664a3d8b6f35

AEST V2 was published[1], add V2 support based on AEST V1.

[1]: https://developer.arm.com/documentation/den0085/latest/

Link: https://github.com/acpica/acpica/commit/ebb4979
Signed-off-by: Ruidong Tian &lt;tianruidong@linux.alibaba.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ACPICA: ACPI 6.5: RAS2: Add support for RAS2 table</title>
<updated>2024-04-12T13:11:24+00:00</updated>
<author>
<name>Shiju Jose</name>
<email>shiju.jose@huawei.com</email>
</author>
<published>2023-09-27T16:41:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=2e94dc11898042eb528eda3e09db242529722916'/>
<id>2e94dc11898042eb528eda3e09db242529722916</id>
<content type='text'>
ACPICA commit c581606cf49b7574d29c02b1a3bc144650375e32

Add support for ACPI RAS2 feature table(RAS2) defined in the ACPI 6.5
Specification &amp; upwards revision, section 5.2.21.

The RAS2 table provides interfaces for platform RAS features. RAS2 offers
the same services as RASF, but is more scalable than the latter.
RAS2 supports independent RAS controls and capabilities for a given RAS
feature for multiple instances of the same component in a given system.
The platform can support either RAS2 or RASF but not both.

Link: https://github.com/acpica/acpica/commit/c581606c
Signed-off-by: Shiju Jose &lt;shiju.jose@huawei.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
ACPICA commit c581606cf49b7574d29c02b1a3bc144650375e32

Add support for ACPI RAS2 feature table(RAS2) defined in the ACPI 6.5
Specification &amp; upwards revision, section 5.2.21.

The RAS2 table provides interfaces for platform RAS features. RAS2 offers
the same services as RASF, but is more scalable than the latter.
RAS2 supports independent RAS controls and capabilities for a given RAS
feature for multiple instances of the same component in a given system.
The platform can support either RAS2 or RASF but not both.

Link: https://github.com/acpica/acpica/commit/c581606c
Signed-off-by: Shiju Jose &lt;shiju.jose@huawei.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ACPI: NHLT: Streamline struct naming</title>
<updated>2024-03-27T15:36:45+00:00</updated>
<author>
<name>Cezary Rojewski</name>
<email>cezary.rojewski@intel.com</email>
</author>
<published>2024-03-19T08:30:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=a640acab545b21ed1f347376f34d34e461ea92ba'/>
<id>a640acab545b21ed1f347376f34d34e461ea92ba</id>
<content type='text'>
Few recently introduced structs are named 'nhlt2' instead of 'nhlt' to
avoid naming conflicts. With duplicate types gone, the conflicts are no
more.

Signed-off-by: Cezary Rojewski &lt;cezary.rojewski@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Few recently introduced structs are named 'nhlt2' instead of 'nhlt' to
avoid naming conflicts. With duplicate types gone, the conflicts are no
more.

Signed-off-by: Cezary Rojewski &lt;cezary.rojewski@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ACPI: NHLT: Drop redundant types</title>
<updated>2024-03-27T15:36:45+00:00</updated>
<author>
<name>Cezary Rojewski</name>
<email>cezary.rojewski@intel.com</email>
</author>
<published>2024-03-19T08:30:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=659a9490ccfbfad4aa5ab351f8a6f5f83ce5ed6c'/>
<id>659a9490ccfbfad4aa5ab351f8a6f5f83ce5ed6c</id>
<content type='text'>
ACPICA commit 0c7379eae2a0342bfc36d6b7db0bb90ad13a5a3e

There are no users for the duplicated NHLT table components.

Link: https://github.com/acpica/acpica/pull/890
Signed-off-by: Cezary Rojewski &lt;cezary.rojewski@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
ACPICA commit 0c7379eae2a0342bfc36d6b7db0bb90ad13a5a3e

There are no users for the duplicated NHLT table components.

Link: https://github.com/acpica/acpica/pull/890
Signed-off-by: Cezary Rojewski &lt;cezary.rojewski@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ACPI: NHLT: Reintroduce types the table consists of</title>
<updated>2024-03-27T15:36:45+00:00</updated>
<author>
<name>Cezary Rojewski</name>
<email>cezary.rojewski@intel.com</email>
</author>
<published>2024-03-19T08:30:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=2f7d7ea44adbe7497b225bbb7bfc29e3c792094d'/>
<id>2f7d7ea44adbe7497b225bbb7bfc29e3c792094d</id>
<content type='text'>
ACPICA commit 32260f5ce519e854546ce907fc0cc449e1fe51fe

Non HDAudio Link Table (NHLT) is designed to separate hardware-related
description (registers) from AudioDSP firmware-related one i.e.:
pipelines and modules that together make up the audio stream on Intel
DSPs. This task is important as same set of hardware registers can be
used with different topologies and vice versa, same topology could be
utilized with different set of hardware. As the hardware registers
description is directly tied to specific platform, intention is to have
such description part of low-level firmware e.g.: BIOS.

The initial design has been provided in early Sky Lake (SKL) days. The
audio architecture goes by the name cAVS. SKL is a representative of
cAVS 1.5. The table helps describe endpoint capabilities ever since.
While Raptor Lake (RPL) is the last of cAVS architecture - cAVS 2.5 to
be precise - its successor, the ACE architecture which begun with
Meteor Lake (MTL) inherited the design for all I2S and PDM
configurations. These two configurations are the primary targets for
NHLT table.

Due to naming conflicts with existing code, several structs are named
'nhlt2' rather than 'nhlt'. Follow up changes clean this up once
existing code has no users and is removed.

Link: https://github.com/acpica/acpica/pull/912
Signed-off-by: Cezary Rojewski &lt;cezary.rojewski@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
ACPICA commit 32260f5ce519e854546ce907fc0cc449e1fe51fe

Non HDAudio Link Table (NHLT) is designed to separate hardware-related
description (registers) from AudioDSP firmware-related one i.e.:
pipelines and modules that together make up the audio stream on Intel
DSPs. This task is important as same set of hardware registers can be
used with different topologies and vice versa, same topology could be
utilized with different set of hardware. As the hardware registers
description is directly tied to specific platform, intention is to have
such description part of low-level firmware e.g.: BIOS.

The initial design has been provided in early Sky Lake (SKL) days. The
audio architecture goes by the name cAVS. SKL is a representative of
cAVS 1.5. The table helps describe endpoint capabilities ever since.
While Raptor Lake (RPL) is the last of cAVS architecture - cAVS 2.5 to
be precise - its successor, the ACE architecture which begun with
Meteor Lake (MTL) inherited the design for all I2S and PDM
configurations. These two configurations are the primary targets for
NHLT table.

Due to naming conflicts with existing code, several structs are named
'nhlt2' rather than 'nhlt'. Follow up changes clean this up once
existing code has no users and is removed.

Link: https://github.com/acpica/acpica/pull/912
Signed-off-by: Cezary Rojewski &lt;cezary.rojewski@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
