I neglected to send Tony the most recent version of the
patch ("Fix Altix BTE error return status") applied
as commit: 64135fa97ce016058f95345425a9ebd04ee1bd2a

This patch gets it up to date.  Without this patch
on shub2, if there is no error xpcBteUnmappedError is
returned instead of xpcSuccess.

Signed-off-by: Russ Anderson (rja@sgi.com)
Signed-off-by: Tony Luck <tony.luck@intel.com>

This fixes an unused variable warning in mm/vmalloc.c.

Tony: also fix resulting fallout in uncached.c with a
typo in args to flush_tlb_kernel_range().

Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>

The Altix shub2 BTE error detail bits are in a different location
than on shub1.  The current code does not take this into account
resulting in all shub2 BTE failures mapping to "unknown".

This patch reads the error detail bits from the proper location,
so the correct BTE failure reason is returned for both shub1
and shub2.

Signed-off-by: Russ Anderson <rja@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>

s/addres/address/
s/performanc/performance/

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>

__clear_bit_unlock does not need to perform atomic operations on the
variable.  Avoid a cmpxchg and simply do a store with release semantics.
Add a barrier to be safe that the compiler does not do funky things.

Tony: Use intrinsic rather than inline assembler

Signed-off-by: Christoph Lameter <clameter@sgi.com>
Acked-by: Nick Piggin <nickpiggin@yahoo.com.au>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Tony Luck <tony.luck@intel.com>

Make some IOSAPIC functions static and remove one that is unused.

Signed-off-by: Simon Horman <horms@verge.net.au>
Signed-off-by: Tony Luck <tony.luck@intel.com>

AMD Opteron processors before CG revision don't like C-states > 1.

This solves the long standing bugzilla #5303 and probably some more
on affected machines:

  http://bugzilla.kernel.org/show_bug.cgi?id=5303

[ tglx@linutronix.de: reworked the patch so it does not wreck ia64 ]

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

Newer Itanium versions have added additional processor feature set
bits.  This patch prints all the implemented feature set bits.  Some
bit descriptions have not been made public.  For those bits, a generic
"Feature set X bit Y" message is printed.  Bits that are not implemented
will no longer be printed.

Signed-off-by: Russ Anderson <rja@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>

there is a typo in the definition of per_cpu_offset because, for ia64,
the __per_cpu_offset is an array.

Signed-off-by: Yu Luming <luming.yu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>

Clean up the process for presenting the "physical id" field in
/proc/cpuinfo.

	- remove global smp_num_cpucores, as it is mostly useless

	- remove check_for_logical_procs(), since we do the same
	  functionality in identify_siblings()

	- reflow logic in identify_siblings(). If an older CPU
	  does not implement PAL_LOGICAL_TO_PHYSICAL, we may still
	  be able to get useful information from SAL_PHYSICAL_ID_INFO

	- in identify_siblings(), threads/cores are a property of
	  the CPU, not the platform

	- remove useless printk's about multi-core / thread
	  capability in identify_siblings(), as that information
	  is readily available in /proc/cpuinfo, and printing for
	  the BSP only adds little value

	- smp_num_siblings is now meaningful if any CPU in the
	  system supports threads, not just the BSP

	- expose "physical id" field, even on CPUs that are not
	  multi-core / multi-threaded (as long as we have a valid
	  value). Now we know what sockets Madisons live in too.

Signed-off-by: Alex Chiang <achiang@hp.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>